參數(shù)資料
型號(hào)： S-4544A
廠商： Seiko Instruments Inc.
英文描述： LCD Controller-Driver With Built-in 8-Bit and Serial Interfaces(內(nèi)置8位和串行接口的LCD控制器-驅(qū)動(dòng)器)
中文描述： LCD控制器與- 8內(nèi)置驅(qū)動(dòng)器位和串行接口（內(nèi)置8位和串行接口的液晶顯示控制器-驅(qū)動(dòng)器）
文件頁(yè)數(shù)： 12/39頁(yè)
文件大小： 237K
代理商： S-4544A
LCD Controller-Driver
S-4544A
Seiko Instruments Inc.
11
5.Chip Select
The MPU interface is turned to “Active” by setting CSK pin to “L”
Table 10 Chip Select Logic
CSX
State
Description
“H”
Standby
D0 to D7 :
A0
RDX
R/WX
High impedance
Invalid
Invalid
Invalid
:
:
:
“L”
Active
All pins are valid
6.Data Bus Select
7.Display Data RAM
The S-4544A has Display Data RAM (8-bits
×
8-pages x 128 columns +128 columns =8320 bits]. It is possible to
use the not-used area for display as normal SRAM. The Display /data RAM is made of dual-port RAM. The
read/write access form the MPU interface is performed independently of the read access to the LC display.
At the moment power is turned on, the contents of the Display Data RAM are uncertain. Following turning on power,
write
“
0
”
in all bits of the Display Data RAM or write the display data with display OFF and then turn the display ON.
8.Reading and Writing Display Data From MPU
The S-4544A reads and writes the display data through the internal bus holder. The display data is read to the bus
holder from the Display Data RAM, and in the next read cycle on the data bus. Therefore, a dummy read cycle is
needed before the first read cycle. When reading the display data after the column address set and the data write
cycle, a dummy read is needed. Since the reading of the display data is executed using this bus holder, it is possible
to read the data at high speed.
Display data is written to the Display Data RAM through the bus holder within a write cycle. Therefore, writing the
display data does not need a dummy cycle.
After executing READ and WRITE commands, the column address is incremented by 1. When the cycle time
represented with timing characteristics is met, READ and WRITE commands can be executed in succession.
Increment of the column address stops at the upper address of the Display Data RAM.
9.Column Address
The column address of the Display Data RAM is used for reading/writing displayed data from/to the MPU. The
column address is set by a command. When the displayed data RAM is accessed by the MPU, the address
increments by one.
68-Family
80-Family
A0
R/WX
RDX
R/WX
1
1
0
1
Reads from Display Data RAM
1
0
1
0
Writes to Display Data RAM
0
1
0
1
Status Read
0
0
1
0
Command Read to internal register
Table 11
Data Bus Select
Description
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