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參數(shù)資料
| 型號： | RK80530KZ017512 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷 |
| 文件頁數(shù)： | 42/86頁 |
| 文件大?。?/td> | 882K |
| 代理商： | RK80530KZ017512 |
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42
Datasheet
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
3.0
Signal Quality Specifications
Signals driven on the processor system bus should meet signal quality specifications to ensure that
the components read data properly and to ensure that incoming signals do not affect the long term
reliability of the component. Specifications are provided for simulation at the processor pins.
Meeting the specifications at the processor pins in
Table 22
,
Table 23
, and
Table 26
ensures that
signal quality effects will not adversely affect processor operation.
3.1
BCLK/BCLK# & PICCLK Signal Quality Specifications and
Measurement Guidelines
Table 23
describes the signal quality specifications at the processor pins for the processor system
bus clock (BCLK/BCLK#) and APIC clock (PICCLK) signals. References made to BCLK signal
quality specifications also applies to BCLK#.
Figure 18
describes the signal quality waveform for
the system bus clock at the processor pins.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Intel Pentium III processors with 512KB L2
cache at all frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/BCLK# and PICCLK signals can dip back to after passing the V
IH
(rising) or V
IL
(falling)
voltage limits. This specification is an absolute value.
Table 22. BCLK (Single-Ended Clock Mode) Signal Quality Specifications for Simulation at
the Processor Pins
1
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1: BCLK V
IL
0.3
V
18
V2: BCLK V
IH
2.2
V
18
V3: BCLK Absolute Voltage Range
-0.5
3.1
V
18
V4: BCLK Rising Edge Ringback
2.0
V
18
2
V5: BCLK Falling Edge Ringback
0.5
V
18
2
Table 23. BCLK/BCLK# (Differential Clock Mode) and PICCLK Signal Quality Specifications
for Simulation at the Processor Pins
1
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1: BCLK V
IL
-0.2
0.35
V
18
V1: PICCLK V
IL
0.40
V
18
V2: BCLK V
IH
0.92
1.45
V
18
V2 PICCLK V
IH
1.60
V
18
V3: BCLK Absolute Voltage Range
-0.2
1.45
V
18
V3: PICCLK Absolute Voltage
Range
-0.4
2.4
V
18
V4: BCLK Rising Edge Ringback
0.35
V
18
2
V4: PICCLK Rising Edge Ringback
1.60
V
18
2
V5: BCLK Falling Edge Ringback
-0.35
V
18
2
V5: PICCLK Falling Edge Ringback
0.40
V
18
2
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