參數(shù)資料
型號(hào)： RK80530KZ017512
英文描述： MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC
中文描述： 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷
文件頁(yè)數(shù)： 21/86頁(yè)
文件大?。?/td> 882K
代理商： RK80530KZ017512
Datasheet
21
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
2.7
Processor System Bus Unused Pins
All RESERVED pins must remain unconnected unless specifically noted. Connection of these pins
to V
CCCORE
, V
REF
, V
SS
, V
TT
or to any other signal (including each other) can result in component
malfunction or incompatibility with future processors. See
Section 5.4
for a pin listing of the
processor and the location of each RESERVED pin.
PICCLK must be driven with a valid clock input and the PICD[1:0] signals must be pulled-up to
V
CCCMOS1.5
even when the APIC will not be used. A separate pull-up resistor must be provided for
each PICD signal.
For reliable operation, always connect unused inputs or bidirectional signals to their deasserted
signal level. The pull-up or pull-down resistor values are system dependent and should be chosen
such that the logic high (V
IH
) and logic low (V
IL
) requirements are met. See
Table 11
for level
specifications of non-AGTL signals.
For unused AGTL inputs, the on-die termination will be sufficient. No external R
TT
is necessary on
the motherboard
For unused CMOS inputs, active low signals should be connected through a pull-up resistor to
V
CCCMOS1.5
and meet V
IH
requirements. Unused active high CMOS inputs should be connected
through a pull-down resistor to ground (V
SS
) and meet V
IL
requirements. Unused CMOS outputs
can be left unconnected. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system testability.
2.8
Processor System Bus Signal Groups
To simplify the following discussion, the processor system bus signals have been combined into
groups by buffer type. All P6 family processor system bus outputs are open drain and require a
high-level source provided termination resistors. However, the Intel Pentium
III
processor with
512KB L2 Cache includes on-die termination for AGTL signals and termination resistors placed on
the platform are not necessary except for the RESET# signal which still requires external
termination.
AGTL input signals have differential input buffers which use V
REF
as a reference signal. AGTL
output signals require termination to 1.25 V. In this document, the term “AGTL Input” refers to the
AGTL input group as well as the AGTL I/O group when receiving. Similarly, “AGTL Output”
refers to the AGTL output group as well as the AGTL I/O group when driving.
The PWRGOOD signal input is a 1.8V signal level and must be pulled up to V
CCCMOS1.8
. The
VTT_PWRGD is
not
1.8V tolerant and must be connected to V
TT
(
1.25V)
.
Other CMOS inputs
(A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and STPCLK#) are
only 1.5 V tolerant and must be pulled up to V
CCCMOS1.5
. The CMOS, APIC, and TAP outputs are
open drain and must be pulled to the appropriate level to meet the input specifications of the
interfacing device.
The groups and the signals contained within each group are shown in
Table 4
. Refer to
Section 7.0
for a description of these signals.
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