- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373275 > RK80530KZ017512 MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC PDF資料下載
參數(shù)資料
| 型號： | RK80530KZ017512 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|PGA|370PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS |美巡賽| 370PIN |陶瓷 |
| 文件頁數(shù)： | 36/86頁 |
| 文件大?。?/td> | 882K |
| 代理商： | RK80530KZ017512 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
36
Datasheet
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
NOTES:
1. All signals, during their invalid states, must be guarded against spurious levels from effecting the platform
during processor power-up sequence.
2. Configuration Input signals include: A[14:5], BR0#, BR1#, INIT#. For timing of these signals, please refer to
Table 17
and
Figure 13
.
Notes:
For
Figure 9
through
Figure 19
, the following apply:
1.
Figure 9
through
Figure 19
are to be used in conjunction with
Table 14
through
Table 20
.
2. All timings for the AGTL signals at the processor pins are referenced to the rising edge of
BCLK and the falling edge of BCLK# at the crossing point for differential clock mode and to
the rising edge of BCLK at BCLK
VREF
(1.25V) for single-ended clock mode. All AGTL signal
timings (address bus, data bus, etc.) are referenced at 2/3 of VTT at the processor pins.
3. All timings for the APIC I/O signals at the processor pins are referenced to the PICCLK rising
edge at 0.9 V. All APIC I/O signal timings are referenced at 1.0 V at the processor pins.
4. All timings for the TAP signals at the processor pins are referenced to the TCK rising edge at
1.0 V. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.0 V at the processor pins.
Table 21. Platform Power-On Timings
2
T# Parameter
Min
Max
Unit
Figure
Notes
T45: Valid Time Before VTT_PWRGD
1.0
mS
14
1
T46: Valid Time Before PWRGOOD
2.0
mS
14
1
T47: RESET# Inactive to Valid Outputs
1
BCLK
14
1
T48: RESET# Inactive to Drive Signals
4
BCLK
14
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RK80532PC041512 | Microprocessor |
| RK9410 | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 7A I(D) | SO |
| RKC-SERIES | Interface IC |
| RKCB-SERIES | Interface IC |
| RKCR-SERIES | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RK80530KZ017512S L5XL | 制造商:Intel 功能描述:32BIT MPU 80530KZ017512 1.40G |
| RK80530KZ017512S L6BY | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.4GHz 370-Pin FCPGA2 |
| RK80530PZ001256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| RK80530PZ006256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| RK80530PZ009256 | 制造商:Rochester Electronics LLC 功能描述:PIII 1.2G 256 ON DIE CACHE FC-PGA2 - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。