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參數(shù)資料
| 型號(hào)： | RD-19240FG-A00 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP52 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, PLASTIC, MQFP-52 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 432K |
| 代理商： | RD-19240FG-A00 |
13
Data Device Corporation
www.ddc-web.com
RD-19240
F-0209-0
TABLE 8. A_QUAD_B FUNCTION
A_QUAD_B
U/B
0
B
1
U
TABLE 9. ZIP_EN FUNCTION
ZIP_EN
CB/ZI
0
ZI
1
CB
encoder resolution latched into the RD-19240 (refer to
FIGURE 18). The calculations for the timing are:
n = resolution of parallel data
t = 1 / ( 2n* Velocity(RPS))
T = 1 / ( Velocity(RPS))
Note: The Z1 pulse is high when all the bits of the counter
are zero. If the resolution of the counter, (parallel data)
is programmed differently than that of the A_QUAD_B
then the resolution of the counter will determine the
resolution of the ZIP.
CLARIFICATION OF A_QUAD_B, U/B AND
ZIP_EN FUNCTIONS
The RD-19240 is a tracking converter designed with a Type II
closed servo loop. The Type II closed servo loop has an internal
incremental integrator. This integrator acts as an up-down posi-
tion counter. An AC error (e) within the RD-19240 represents the
difference between
θ (current angle to be digitized) and φ (the
angle stored in digital form in the up-down counter). Because the
RD-19240 constitutes in itself a Type II closed loop servomech-
anism, it continuously attempts to null the error to zero. This is
accomplished by counting up or down 1 LSB until
φ is equal to θ
thus having an error of zero.
When A_QUAD_B is logic 0, encoder emulation mode is select-
ed (i.e. The U/B output is programmed to B). The encoder emu-
lator resolution is set on the falling edge of A_QUAD_B (see
TABLE 8).
When A_QUAD_B is logic 1, encoder emulation mode is not
selected (i.e. The U/B output is set to U, which indicates the
direction of the internal position counter).
2t
B(X- or LSB & LSB+1)
A (LSB+1)
ZIP (NRP)
359.95
0
T
t
FIGURE 18. INCREMENTAL ENCODER EMULATION
Note: U indicates the direction of the counter. It stands for
“UP”. If the RD-19240 is at a static angle awaiting a
new angle
θθ,, U indicates the direction the counter was
going to get to the current angle
φφ. As the error is
approaching zero, the internal analog circuitry voltage
may overshoot before settling - which would then indi-
cate an incorrect direction. Because of this overshoot,
the U output should not be relied on after settling to a
static state. Only during active resolver movement will
the U output state be reliable. U is a logic 1 when
going in the positive direction (increasing angle). It is
a logic 0 when going in the negative direction
(decreasing angle).
ZIP_EN chooses between the CB and Zero Index pulse outputs
and is independent of encoder emulation mode. A logic 1
enables the CB pulse, a logic 0 enables the Zero Index pulse
(see TABLE 9).
Note: When the RD-19240 is set for 14-bit mode, the LSB is
bit 14. When the RD-19240 is set for 12-bit mode, the
LSB is bit 12 and bits 13 and 14 are set to logic “0”.
(See TABLE 1, NOTE 1).
EVALUATION CARD
The RD-19240 can be easily evaluated using the RD-19240EX-
300 evaluation card. A manual for this evaluation card is available
for download from www.ddc-web.com.
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