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參數(shù)資料
| 型號： | RD-19240FG-A00 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP52 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, PLASTIC, MQFP-52 |
| 文件頁數(shù)： | 19/19頁 |
| 文件大?。?/td> | 432K |
| 代理商： | RD-19240FG-A00 |
9
Data Device Corporation
www.ddc-web.com
RD-19240
F-0209-0
R1
R 3
R 2
R 4
EXTERNAL
REF
LO
HI
RESOLVER
S4
S3
S1
S2
GND
+S
-S
SIN
COS
-C
+C
A GND
-R
+R
Notes:
1) Resistors selected to limit Vref peak to between 1.5 V and 5 V.
2) If external reference LO is grounded, then R3 and R4 are not
needed, and -R is connected to GND.
3) 10k ohms, 1 % series current limit resistors are recommended.
See Note 3.
Note: Five external BW components
as shown in Figures 1 and 2
are necessary for the R/D to
function.
FIGURE 9. TYPICAL CONNECTIONS, 2 VOLT
RESOLVER, DIRECT INPUT
GND
UP/DN
SHIFT
RD-19240
D1
D0
CONTROL
FIGURE 8. INPUT WIRING - SWITCHING-ON-THE-FLY
BETWEEN 10- AND 12-BIT RESOLUTION
3) UP/DN will program the gain of the pre-charged components/
amplifier (see TABLE 5). If the resolution is going to increase
(UP/DN logic 0), the gain of the pre-charge amplifier will be set
to 4. If the resolution is going to decrease (UP/DN logic 1), the
gain of the pre-charge amplifier will be set to 1/4. The gain of
the pre-charge amplifier should be programmed prior to
switching the resolution of the converter, allowing enough time
for the components to settle to the pre-charged level. This time
will depend on the time constant of the bandwidth compo-
nents being charged. If switching is limited to two adjacent res-
olutions (i.e., 12 and 14) then the pre-charge amplifier can be
set up to continuously maintain the appropriate velocity volt-
age on the deselected components, resulting in the fastest
possible switching times. See FIGURE 8 for an example of the
input wiring connections necessary for switching-on-the-fly
between 10 and 12 bit resolution.
DUAL BANDWIDTHS
With the second set of BW component pins, the user can set two
bandwidths for the RD-19240 and choose between them. To use
two bandwidths, proceed as follows:
1) Tie UP/DN pin to -5V.
2) Choose the two bandwidths following the guidelines in the
General Setup Considerations; the RV resistor must be the
same value for both bandwidths.
3) Use the SHIFT pin to choose between bandwidths. A logic 1 selects
the VEL1 components and a logic 0 selects the VEL2 components.
SYNTHESIZED REFERENCE
The synthesized reference section of the RD-19240 eliminates
errors due to phase shift between the reference and signal inputs.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage (e)
in the converter. Due to the inductive nature of synchros and
resolvers, their output signals lead the reference input signal (RH
and RL). When an uncompensated reference signal is used to
demodulate the control transformer’s output, quadrature voltages
are not completely eliminated. As shown in the block diagram,
FIGURE 1, the converter synthesizes its own internal reference
signal based on the SIN and COS signal inputs. Therefore, the
phase of the synthesized (internal) reference is determined by the
signal input, resulting in reduced quadrature errors.
TYPICAL INPUT CONFIGURATION
FIGURE 9 illustrates a typical input configuration for a 2 Volt
Resolver input. However, other configurations may be used. Consult
the RD/RDC Series Converters Applications Manual (document
#MN-19220XX-001) for additional input configuration options.
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