
R01UH0218EJ0110 Rev.1.10
Page 166 of 664
Sep 12, 2011
R32C/142 Group and R32C/145 Group
10. Interrupts
10.13 Intelligent I/O Interrupt
The intelligent I/O interrupt is assigned to software interrupt numbers 44 to 55.
Figure 10.15 shows a block diagram of the intelligent I/O interrupt. Figure 10.16 and Figure 10.17 show
registers IIOiIR and IIOiIE (i = 0 to 11), respectively.
To use the intelligent I/O interrupt, the IRLT bit in the IIOiIE register should be set to 1 (interrupt requests
used for interrupt).
The intelligent I/O interrupt has multiple request sources. When an interrupt request is generated with an
intelligent I/O function, the corresponding bit in the IIOiIR register becomes 1 (interrupt requested). If the
corresponding bit in the IIOiIE register is set to 1 (interrupt enabled), the IR bit in the corresponding IIOiIC
register changes to 1 (interrupt requested).
After the IR bit setting changes from 0 to 1, it remains unchanged if a bit in the IIOiIR register becomes 1
by another interrupt request source and the corresponding bit in the IIOiIE register is 1.
Bits in the IIOiIR register do not become 0 even if an interrupt is accepted. They should be set to 0 by
either the AND or BCLR instruction. Note that every generated interrupt request is ignored until these bits
are set to 0.
To use the intelligent I/O interrupt to activate DMAC II, the IRLT bit in the IIOiIE register should be set to 0
(interrupt requests used for DMA or DMA II) and the bit used for the interrupt source in the IIOiIE register
should be set to 1 (interrupt enabled).
Figure 10.15 Intelligent I/O Interrupt Block Diagram (i = 0 to 11)
Bit 1
0
1
Bit 2
0
1
Bit 7
0
1
IIOiIR register (2)
Bit 1
Bit 2
Bit 7
IIOiIE register (3)
Intelligent I/O
interrupt i request
IRLT bit in the
IIOiIE register
Interrupt request (1)
Notes:
1. Refer to Figures 10.16 and 10.17 for bits 1
to 7 in registers IIOiIR and IIOiIE and their
respective interrupt request sources.
2. Bits 1 to 7 in the IIOiIR register do not
become 0 even if an interrupt request is
accepted. They should be set to 0 by a
program.
3. The IRLT bit and the interrupt enable bit in
the IIOiIE register should not be rewritten
simultaneously.