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參數(shù)資料
| 型號(hào)： | R5F3650NNFB |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, LQFP-100 |
| 文件頁(yè)數(shù)： | 30/81頁(yè) |
| 文件大?。?/td> | 879K |
| 代理商： | R5F3650NNFB |
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48
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
Figure 9-3.
MCU Start-up, RESET Extended Externally
9.0.4
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see Table 9-1) will generate a reset, even if the clock is not running.
Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the
Reset Threshold Voltage – V
RST – on its positive edge, the delay counter starts the MCU after
the Time-out period – t
TOUT – has expired.
Figure 9-4.
External Reset During Operation
9.0.5
Brown-out Detection
AT90PWM2/2B/3/3B has an On-chip Brown-out Detection (BOD) circuit for monitoring the V
CC
level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can
be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free
Brown-out Detection. The hysteresis on the detection level should be interpreted as V
BOT+ =
V
BOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
VCC
CC
Table 9-2.
BODLEVEL Fuse Coding
BODLEVEL 2..0 Fuses
Min VBOT
Typ VBOT
Max VBOT
Units
111
BOD Disabled
110
4.5
V
101
2.7
V
100
4.3
V
011
4.4
V
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