
R01DS0031EJ0200 Rev.2.00
Page 2 of 111
Feb 07, 2011
M16C/65 Group
1. Overview
1.2
Specifications
The M16C/65 Group includes 128-pin and 100-pin packages. Table 1.1 to
Table 1.4 list specifications.
Table 1.1
Specifications for the 128-Pin Package (1/2)
Item
Function
Description
CPU
Central processing unit
M16C/60 Series core
(multiplier: 16 bit × 16 bit
32 bit,
multiply and accumulate instruction: 16 bit × 16 bit + 32 bit
32 bit)
Number of basic instructions: 91
Minimum instruction execution time:
31.25 ns (f(BCLK) = 32 MHz, VCC1 = VCC2 = 2.7 to 5.5 V)
Operating modes: Single-chip, memory expansion, and microprocessor
Memory
ROM, RAM, data flash
Voltage
Detection
Voltage detector
Power-on reset
3 voltage detection points (detection level of voltage detection 0 and 1
selectable)
Clock
Clock generator
5 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz),
high-speed on-chip oscillator (40 MHz ±10%), PLL frequency synthesizer
Oscillation stop detection: Main clock oscillation stop/restart detection
function
Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16
Power saving features: Wait mode, stop mode
Real-time clock
External Bus
Expansion
Bus memory expansion
Address space: 1 MB
External bus interface: 0 to 8 waits inserted, 4 chip select outputs,
memory area expansion function (expandable to 4 MB), 3 V and 5 V
interfaces
Bus format: Separate bus or multiplexed bus selectable, data bus width
selectable (8 or 16 bits), number of address buses selectable (12, 16, or
20)
I/O Ports
Programmable I/O ports
CMOS I/O ports: 111 (selectable pull-up resistors)
N-channel open drain ports: 3
Interrupts
Interrupt vectors: 70
External interrupt inputs: 13 (NMI, INT × 8, key input × 4)
Interrupt priority levels: 7
Watchdog Timer
15-bit timer × 1 (with prescaler)
Automatic reset start function selectable
DMA
DMAC
4 channels, cycle steal mode
Trigger sources: 43
Transfer modes: 2 (single transfer, repeat transfer)