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參數(shù)資料
| 型號： | R5F3650NNFB |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, LQFP-100 |
| 文件頁數(shù)： | 29/81頁 |
| 文件大?。?/td> | 879K |
| 代理商： | R5F3650NNFB |
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47
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
Notes:
1. Values are guidelines only..
2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)
9.0.3
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 9-1. The POR is activated whenever V
CC is below the detection level. The
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
CC rise. The RESET signal is activated again, without any delay,
when V
CC decreases below the detection level.
Figure 9-2.
MCU Start-up, RESET Tied to V
CC
Table 9-1.
Reset Characteristics(1)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VPOT
Power-on Reset Threshold
Voltage (rising)
1.4
2.3
V
Power-on Reset Threshold
Voltage (falling)(2)
1.3
2.3
V
VRST
RESET Pin Threshold Voltage
0.2Vcc
0.85Vcc
V
tRST
Minimum pulse width on RESET
Pin
400
ns
VPOR
VCC start voltage to ensure
internal Power-on RESET signal
-0.05
GND
+0.05
V
CCRR
VCC Rise Rate to ensure internal
Power-on RESET signal
0.3
V/ms
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
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