參數(shù)資料
型號(hào): R5F363A6NFA
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 84/115頁
文件大?。?/td> 2363K
代理商: R5F363A6NFA
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 70 of 113
M16C/63 Group
5. Electrical Characteristics
VCC1 = VCC2 = 5 V
Timing Requirements
(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
5.2.3
Timing Requirements (Memory Expansion Mode and Microprocessor
Mode)
Notes:
1.
Calculated according to the BCLK frequency as follows:
2.
Calculated according to the BCLK frequency as follows:
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
3.
Calculated according to the BCLK frequency as follows:
n is 2 for 2 waits setting, and 3 for 3 waits setting.
4.
Calculated according to the BCLK frequency as follows:
n is 3 for 2
φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.
Table 5.34
Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Unit
Min.
Max.
tac1(RD-DB)
Data input access time (for setting with no wait)
ns
tac2(RD-DB)
Data input access time (for setting with 1 to 3 waits)
ns
tac3(RD-DB)
Data input access time (when accessing multiplex bus area)
ns
tac4(RD-DB)
Data input access time (for setting with 2
φ + 3φ or more)
ns
tsu(DB-RD)
Data input setup time
40
ns
tsu(RDY-BCLK)
RDY input setup time
30
ns
tsu(HOLD-BCLK)
HOLD input setup time
40
ns
th(RD-DB)
Data input hold time
0ns
th(BCLK-RDY)
RDY input hold time
0ns
th(BCLK-HOLD)
HOLD input hold time
0ns
0.5
10
9
×
f
BCLK
()
----------------------45 ns
[]
n
0.5
+
() 10
9
×
f
BCLK
()
------------------------------------
45 ns
[]
n
0.5
() 10
9
×
f
BCLK
()
------------------------------------45 ns
[]
n
10
9
×
f
BCLK
()
------------------45 ns
[]
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