參數(shù)資料
型號： R5F2L387CDFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 69/74頁
文件大?。?/td> 959K
代理商： R5F2L387CDFP
72
2588F–AVR–06/2013
ATtiny261/461/861
visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the
Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure.
In 16-bit mode one more 8-bit register is available, the Timer/Counter0 High Byte Register
(TCNT0H). Also, in 16-bit mode, there is only one output compare unit as the two Output Com-
pare Registers, OCR0A and OCR0B, are combined to one, 16-bit Output Compare Register,
where OCR0A contains the low byte and OCR0B contains the high byte of the word. When
accessing 16-bit registers, special procedures described in section “Accessing Registers in 16-
bit Mode” on page 80 must be followed.
11.2.2
Definitions
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e. TCNT0L for accessing
Timer/Counter0 counter value, and so on.
The definitions in Table 11-1 are also used extensively throughout the document.
11.3
Clock Sources
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic is controlled by the Clock Select (CS02:0) bits located in the
Timer/Counter Control Register 0 B (TCCR0B), and controls which clock source and edge the
Timer/Counter uses to increment its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
T0).
11.3.1
Prescaler
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
CLK_I/O). Alternatively, one of four taps from the prescaler can be used as a
clock source.
See Figure 11-2 for an illustration of the prescaler unit.
Table 11-1.
Definitions
Constant
Description
BOTTOM
The counter reaches BOTTOM when it becomes 0x00
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255)
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the
value stored in the OCR0A Register. The assignment depends on the mode of operation
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