參數(shù)資料
型號(hào)： R5F2L387CDFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 48/74頁(yè)
文件大?。?/td> 959K
代理商： R5F2L387CDFP
53
2588F–AVR–06/2013
ATtiny261/461/861
Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-
ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even
if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from the INT0 Interrupt Vector.
Bit 5 – PCIE1: Pin Change Interrupt Enable
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt is enabled. Any change on any enabled PCINT7:0 or PCINT15:12 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI Interrupt Vector. PCINT7:0 and PCINT15:12 pins are enabled individually by the
PCMSK0 and PCMSK1 Register.
Bit 4 – PCIE0: Pin Change Interrupt Enable
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt is enabled. Any change on any enabled PCINT11:8 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt
Vector. PCINT11:8 pins are enabled individually by the PCMSK1 Register.
Bits 3:0 – Res: Reserved Bits
These bits are reserved and will always read as zero.
9.3.3
GIFR – General Interrupt Flag Register
Bit 7 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set
(one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT1 is configured as a level interrupt.
Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT15 pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
Bits 4:0 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bit
7654
3210
INT1
INTF0
PCIF
–
––––GIFR
Read/Write
R/W
R
Initial Value
0000
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