
R8C/38T-A Group
20. Serial Interface (UART2)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 409 of 730
Aug 05, 2011
20.2.5
UART2 Transmit/Receive Control Register 1 (U2C1)
Notes:
1. The RI bit is set to 0 (no data in the U2RB register) when the U2RB register is read.
2. Set to 1 (transmission completed) when in I2C mode.
3. Can only be set in clock synchronous serial I/O mode (SIO mode). In other modes, set this bit to 0 (continuous
receive mode disabled).
4. Can only be set in SIO/UART mode. In other modes, set this bit to 0 (not inverted).
5. Set to 0 (output disabled).
Write to the U2C1 register using the MOV instruction.
This bit inverts the polarity of transmit data and receive data (data only). When the U2LCH bit is 1 (inverted),
the logic of data written to the U2TB register is inverted when writing data to the U2TB register during
transmission. When reading data from the U2TB register during reception, data with inverted logic is read.
Address 000C5h
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0010
Bit
Symbol
Bit Name
Function
R/W
b0
TE
Transmission enable bit
0: Transmission disabled
1: Transmission enabled
R/W
b1
TI
Transmit buffer empty flag
0: Data present in the U2TB register
1: No data in the U2TB register
R
b2
RE
Reception enable bit
0: Reception disabled
1: Reception enabled
R/W
b3
RI
Reception complete flag
(1)0: No data in the U2RB register
1: Data present in the U2RB register
R
b4
U2IRS
UART2 transmit interrupt source
0: Transmit buffer empty (TI = 1)
1: Transmission completed (TXEPT = 1)
R/W
b5
U2RRM
UART2 continuous receive mode
0: Continuous receive mode disabled
1: Continuous receive mode enabled
R/W
b6
U2LCH
Data logic select bit
0: Not inverted
1: Inverted
R/W
b7
U2ERE
Error signal output enable bit
(5)0: Output disabled
1: Do not set.
R/W