
R8C/38T-A Group
16. Timer RB2
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 262 of 730
Aug 05, 2011
Figure 16.5
Example of 16-Bit Timer Operation in Programmable Waveform Generation Mode
TRBPRE is reloaded
(simultaneously with TRBPR/TRBSC reload)
TOPL bit in
TRBIOC register
TSTART bit in
TRBCR register
Count source
Counter input
TCSTF bit in
TRBCR register
TRBPR register
TRBSC register
TRBPR
count register
TRBPRE
count register
TRBPR/TRBSC
reload register
load signal
TRBPRE
reload register
load signal
TRBO output pin
Interrupt request
one-shot signal
TRBPRE register
00h
01h
00h
02h
01h
00h
FEh
01h
FFh
00h
01h
00h
FFh
FFh
FFh
0: High output during primary period, low output during secondary period, low output at timer stop
Set to 1 by a program
Synchronized with the peripheral system clock
Decrement
starts
01h
02h
01h
Higher 8-bit decrement
Lower 8-bit decrement
(16-bit decrement)
00FFh
0000h
0201h
01FFh
00FFh
0000h
0101h
TRBSC
is reloaded
TRBPR
is reloaded
TRBPRE
is reloaded
Primary period
Secondary period
Set to 0 by acknowledgment
of an interrupt request
or by a program
Higher 8 bits in the TRBSC register
Lower 8 bits in the TRBPRE register
Higher 8 bits in the TRBPR register
Lower 8 bits in the TRBPRE register
The above diagram applies under the following conditions:
TRBPRE register = 01h, TRBPR register = 01h, TRBSC register = 02h
TCNT16 bit in TRBMR register = 1 (16-bit timer)
TOPL bit = 0 (high output during primary period, low output during secondary period, low output at timer stop),
TOCNT bit = 0 (waveform output) in TRBIOC register
TRBIE bit in TRBIR register = 1 (timer RB2 interrupt enabled)
Set to 1 by a program
Synchronized with the peripheral system clock
Primary period
00h
01h
00h
0101h
01FFh
00h
02h
When registers TRBPR, TRBSC, and TRBPRE
are written while the count is stopped, values
are written to both the reload register and
counter