
R8C/38T-A Group
17. Timer RC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 293 of 730
Aug 05, 2011
17.2.11 Timer RC Output Enable Register (TRCOER)
Address 0014Ah (TRCOER_0)
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
111
1111
Bit
Symbol
Bit Name
Function
R/W
b0
EA
TRCIOA output disable bit [When the OPE bit in the TRCOPR register is 0 (output
waveform manipulation disabled)]
0: TRCIOi pin (i = A or B) output enabled (according to
settings of registers TRCMR and TRCIOR0)
1: TRCIOi pin output disabled (regardless of settings of
registers TRCMR and TRCIOR0)
[When the OPE bit in the TRCOPR register is 1 (output
waveform manipulation enabled)]
0: TRCIOi pin output enabled (according to settings of
registers TRCMR and TRCIOR0)
1: TRCIOi pin output level is fixed depending on setting of
TRCOPR register
R/W
b1
EB
TRCIOB output disable bit
R/W
b2
EC
TRCIOC output disable bit [When the OPE bit in the TRCOPR register is 0 (output
waveform manipulation disabled)]
0: TRCIOk pin (k = C or D) output enabled (according to
settings of registers TRCMR and TRCIOR1)
1: TRCIOk pin output disabled (regardless of settings of
registers TRCMR and TRCIOR1)
[When the OPE bit in the TRCOPR register is 1 (output
waveform manipulation enabled)]
0: TRCIOk pin output enabled (according to settings of
registers TRCMR and TRCIOR1)
1: TRCIOk pin output level is fixed depending on setting of
TRCOPR register
R/W
b3
ED
TRCIOD output disable bit
R/W
b4
—
Nothing is assigned. The write value must be 1. The read value is 1.
—
b5
—
b6
—
b7
PTO
Timer output disable bit
[When the OPE bit in the TRCOPR register is 0 (output
waveform manipulation disabled)]
0: Timer output disabled is invalid
1: Timer output disabled is valid (when a low level is input to
the INT0 pin, bits EA to ED are set to 1 (output disabled))
[When the OPE bit in the TRCOPR register is 1 (output
waveform manipulation enabled)]
The function of the PTO bit is disabled. This bit can be read or
written.
R/W