
R8C/38T-A Group
16. Timer RB2
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 250 of 730
Aug 05, 2011
16.3.1
Timer RB2 Control Register (TRBCR)
Notes:
2. When 1 (count is forcibly stopped) is written to the TSTOP bit, the counter, registers TRBPRE, TRBPR, and
TRBSC, bits TSTART and TCSTF, and bits TOSST, TOSSP, and TOSSTF in the TRBOCR register are initialized.
The TRBO output is also initialized. For details on the initial state of the TRBO output, refer to 16.5.3 TOCNT Bit Count operation is started by writing 1 to the TSTART bit and stopped by writing 0. When the TSTART bit is
set to 1 (count starts), the TCSTF bit is set to 1 (count in progress) in synchronization with the count source.
Also, after 0 is written to the TSTART bit, the TCSTF bit is set to 0 (count stops) in synchronization with the
[Conditions for setting to 0]
When 0 is written to the TSTART bit (the TCFTF bit is set to 0 in synchronization with the count source).
When 1 is written to the TSTOP bit.
[Condition for setting to 1]
When 1 is written to the TSTART bit (the TCFTF bit is set to 1 in synchronization with the count source).
Address 00130h (TRBCR_0)
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0000
Bit
Symbol
Bit Name
Function
R/W
b0
TSTART Timer RB2 count start bit
[When the TMOD1 bit in the TRBMR register is 0]
0: Count stops
1: Count starts
[When the TMOD1 bit in the TRBMR register is 1]
0: Count stops
1: Count enabled
R/W
b1
TCSTF
Timer RB2 count status flag
[When the TMOD1 bit in the TRBMR register is 0]
0: Count stops
1: Count in progress
[When the TMOD1 bit in the TRBMR register is 1]
0: Count stops
1: Count enabled
R
b2
TSTOP
Timer RB2 count forced stop bit
(2)When 1 is written to this bit, the count is forcibly
stopped. The read value is 0.
R/W
b3
—
Nothing is assigned. The write value must be 0. The read value is 0.
—
b4
—
b5
—
b6
—
b7
—