
Rev. 1.00 Mar. 18, 2008 Page xviii of xxiv
14.9.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ..................................................................... 423
14.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 423
14.9.6 SCI Operations during Mode Transitions ............................................................. 424
14.9.7 Notes on Switching from SCK Pins to Port Pins .................................................. 427
14.9.8 Note on Writing to Registers in Transmission, Reception,
and Simultaneous Transmission and Reception.................................................... 428
Section 15 Serial Communication Interface with FIFO (SCIF) ........................ 429
15.1
Features.............................................................................................................................. 429
15.2
Input/Output Pins ...............................................................................................................431
15.3
Register Descriptions ......................................................................................................... 432
15.3.1 Receive Shift Register (FRSR) ............................................................................. 433
15.3.2 Receive Buffer Register (FRBR) .......................................................................... 433
15.3.3 Transmitter Shift Register (FTSR)........................................................................ 434
15.3.4 Transmitter Holding Register (FTHR).................................................................. 434
15.3.5 Divisor Latch H, L (FDLH, FDLL) ...................................................................... 434
15.3.6 Interrupt Enable Register (FIER).......................................................................... 435
15.3.7 Interrupt Identification Register (FIIR)................................................................. 436
15.3.8 FIFO Control Register (FFCR)............................................................................. 438
15.3.9 Line Control Register (FLCR) .............................................................................. 439
15.3.10 Modem Control Register (FMCR)........................................................................ 440
15.3.11 Line Status Register (FLSR)................................................................................. 442
15.3.12 Modem Status Register (FMSR)........................................................................... 446
15.3.13 Scratch Pad Register (FSCR)................................................................................ 447
15.3.14 SCIF Control Register (SCIFCR) ......................................................................... 448
15.4
Operation ........................................................................................................................... 450
15.4.1 Baud Rate ............................................................................................................. 450
15.4.2 Operation in Asynchronous Communication........................................................ 451
15.4.3 Initialization of the SCIF ...................................................................................... 452
15.4.4 Data Transmission/Reception with Flow Control................................................. 455
15.4.5 Data Transmission/Reception Through the LPC Interface ................................... 461
15.5
Interrupt Sources................................................................................................................ 464
15.6
Usage Note......................................................................................................................... 464
15.6.1 Power-Down Mode When LCLK is Selected for SCLK ...................................... 464
Section 16 I
2C Bus Interface (IIC).....................................................................465
16.1
Features.............................................................................................................................. 465
16.2
Input/Output Pins ...............................................................................................................468
16.3
Register Descriptions ......................................................................................................... 469