參數(shù)資料
型號(hào): PXASCCKFBE
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: CMOS 16-bit communications microcontroller
中文描述: 16-BIT, 30 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, SOT-407-1, LQFP-100
文件頁(yè)數(shù): 38/42頁(yè)
文件大小: 229K
代理商: PXASCCKFBE
Philips Semiconductors
Preliminary specification
XA-SCC
CMOS 16-bit communications microcontroller
1999 Mar 29
38
ClkOut
t
CHAV
A
RAS
CASL
OE
D7–D0
4 Byte Fetch is shown on 8 bit bus, burst can be 2 to 16 bytes.
NOTE 4: To meet hold time, EDO DRAM drives Data until OE rises, or until a new falling edge of CAS.
Data Bus is sampled on rising edge of clock 6, and every 2 clocks thereafter (clocks 6, 8, 10, and 12 in this example).
SU01142
1
2
3
4
5
6
7
8
9
10
11
12
RAS ADDRESS
CAS ADDR
(EVEN)
CAS ADDR
(ODD)
CAS ADDR
(EVEN)
CAS ADDR
(ODD)
DRIVEN
BY XA
DRIVEN BY SLAVE
LS BYTE
MS BYTE
LS BYTE
MS BYTE
t
CHAH
t
CHSL
t
AVSL
t
CHSH
t
CHSH
t
CPWH
t
CPWL
t
AVSL
t
CHSL
NOTE 3
NOTE 4
t
CHSH
NOTE 4
t
OHDE
t
DIS
Figure 21. EDO DRAM Burst Code Fetch on 8 Bit Bus
CLKOUT
A
RAS (CS)
CASL
WE
D[7:0]
SU01143
RAS ADDRESS
CAS ADDRESS (EVEN)
CAS ADDRESS (ODD)
t
CHAV
t
CHAV
t
CHSL
t
CHAV
t
CHAV
t
CHSL
t
CHAH
t
AVSL
t
CHAH
t
CHAH
t
CHSH
t
CHSH
t
CPWH
t
DVSL
t
AVSL
t
CHSL
t
DVSL
MS BYTE
LS BYTE
Figure 22. DRAM 16 Bit Write on 8 Bit Bus (FPM or EDO DRAMs)
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