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| 型號(hào)： | PXASCCKFBE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS 16-bit communications microcontroller |
| 中文描述： | 16-BIT, 30 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 21/42頁 |
| 文件大?。?/td> | 229K |
| 代理商： | PXASCCKFBE |
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Philips Semiconductors
Preliminary specification
XA-SCC
CMOS 16-bit communications microcontroller
1999 Mar 29
21
Table 3. Memory Interface Control Registers
Register Name
Reg
Type
Description
MRBH
“MMR Base Address”
High
SFR
8 bits
This SFR is used to relocate the MMRs. It contains address bits a23–a16 of the
base address for the 4 KByte Memory Mapped Register space. See XA-SCC User
Manual for using this SFR to relocate the MMRs.
MRBL
“MMR Base Address” Low
SFR
8 bits
Contains address bits a15–a12 of the base address for the 4 KByte Memory
Mapped Register space.
MICFG
MIF Configuration
MMR
8 bits
Contains the CLKOUT Enable bit.
MBCL
Memory Bank
Configuration Lock
MMR
8 bits
Contains the bits for locking and unlocking the BiCFG Registers.
BiCFG
Bank i Configuration
MMR
8 bits
Contains the size, type, bus width, and enable bits for Memory Bank i.
BiAM
Bank i Base
Address/DRAM Address
Multiplexer Control
MMR
8 bits
Contains the base address bits and DRAM address multiplex control bits for
Memory Bank i.
BiTMG
Bank i Timing
MMR
8 bits
Contains the timing control bits for Memory Bank i.
RFSH
Refresh Timing
MMR
8 bits
Contains the refresh time constant and DRAM Refresh Timer enable bit.
Eight Channel DMA Controller
The XA-SCC has eight DMA channels; one Rx DMA channel
dedicated to each SCC Receive (Rx) channel, and one Tx DMA
channel dedicated to each SCC Transmit (Tx) channel. All DMA
channels are optimized to support memory efficient circular data
buffers in external memory. All DMA channels can also support
traditional linear data buffers.
Transmit DMA Channel Modes
The four Tx channels have four DMA modes specifically designed
for various applications of the attached SCCs. These modes are
summarized in the following table. Full details for all DMA functions
can be found in the DMA chapter of the XA-SCC User Manual.
Table 4. Tx DMA Modes Summary
Mode
Byte Count Source
Maskable Interrupt
Description
Non-SDLC/HDLC
Tx Chaining
Header in memory
On stop
DMA channel picks up header from memory at
end of transmission. If byte count in header is
greater than zero, then DMA transmits the
number of bytes specified in the byte count. If
byte count equals 0, then a maskable interrupt is
generated. This process repeats until byte count
in data header is zero. See XA-SCC User
manual for details.
SDLC/HDLC
Tx Chaining
Header in memory
End of packet (not
end of fragment)
Same as above, except DMA header
distinguishes between fragment of packet and
full pack. See XA-SCC User manual for details.
Stop on TC
Processor loads Byte Count
Register (for each fragment)
Byte count completed
(Tx DMA stops)
Processor loads byte count into DMA. DMA
sends that number of bytes, generates maskable
interrupt, and stops.
Periodic Interrupt
Processor loads Byte Count
Register (only once)
Each time byte count
completed (Tx DMA
continues)
DMA runs until commanded to stop by
processor. Everytime byte counter rolls over, a
new maskable interrupt is generated.
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