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| 型號(hào)： | PXAC37KFA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-bit microcontroller family(16位微控制器系列) |
| 中文描述： | 16-BIT, OTPROM, 32 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 54/68頁(yè) |
| 文件大小： | 344K |
| 代理商： | PXAC37KFA |
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Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
47
At the start of a non–Fragmented message, prior to writing any data
bytes, the DMA will begin by writing 01h into the first byte of the
buffer (byte 0). Once the complete frame has been stored, the DMA
will write the frame information into byte 0, with bits [5] and [4]
always set to ‘1’.
When the application wants to read from the object’s buffer, it can
read byte 0 to determine if the DMA is currently updating the buffer.
If byte 0 contains 01h, then the buffer is currently being updated.
The application should not continue to read from the buffer.
When the application starts to read from the buffer, it should set the
semaphore to 10b. After reading is finished, the application should
check the semaphore again. If it is still 10b, everything is OK.
If, however, the semaphore becomes 01b or 11b after the CPU
access is finished, it means that either the buffer is currently being
accessed by DMA or has been accessed by DMA during the time
the CPU was performing reads. In either case, the CPU should wait
until the semaphore bits become 11b again, and reread.
Use of the semaphore bits is not mandatory. However, their use may
help to maintain data consistency.
There are no dedicated semaphore bits for use with Fragmented
messages. In the case of a Fragmented message (in DeviceNet
only), the DMA will write a 00h in byte 0 of the object’s buffer. After
the completion of a CTL message, the byte count (1 to 255) will be
written to byte 0.
Avoiding Data Corruption for Transmit Message Objects
To avoid data corruption when transmitting messages, there are
three possible approaches:
1. If the Message Complete interrupt is enabled for the transmit
message, the User application would write to the transmit buffer
after seeing the interrupt. Once the interrupt flag is set, it is
known for sure that the pending message has already been
transmitted.
2. Wait until OBJ_EN clears before writing to the buffer. This can be
done by polling the OBJ_EN bit.
3. Clear OBJ_EN, while the object is still in pre–arbitration.
In the first two cases, the pending message will be transmitted
completely before the next message gets sent. For the third case,
the message will not be transmitted. Instead, a message with new
content will enter pre–arbitration.
There is an additional mechanism that prevents corruption of a
message that is being transmitted. If a transmission is ongoing for a
Message Object, the XA-C3 hardware will prevent the User from
clearing the OBJ_EN bit in the object’s MnCTL register.
OSEK, DEVICENET, AND CANOPEN FRAMES OF INTEREST
OSEK ConsecutiveFrame
Data Byte
Bit 7
Bit 6
2 – DLC
1
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User Data
1
0
SN
DeviceNet I/O Message
Data Byte
2 – DLC
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User Data
Fragment Type
Fragment Count
Fragment Type = 00
Fragment Count = 0 ... This is the First Fragment
Fragment Count = 3F ... This is both the First and Last Fragment
Fragment Type = 01 ... Middle Fragment
Fragment Type = 10 ... Last Fragment
CANopen Download Domain Segment Request
Data Byte
Bit 7
2 – DLC
1
ccs (User specified)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User Data
t
n (User specified)
c
c = 0 ... not last segment
c = 1 ... last segment
CANopen Auto–Acknowledge Tx Response to Download Domain Segment
Data Byte
Bit 7
Bit 6
2 – 8
1
scs (User specified)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
reserved
t
not used, always 0000
CAN/CTL RELATED INTERRUPTS
The CAN/CTL module will generate five different Event interrupts to
the XA core:
Rx Message Complete
Tx Message Complete
Rx Buffer Full
Message Error
Frame Error
Rx and Tx Message Complete Interrupts
In the following discussion (and elsewhere in the document) the
term “message” applies to a complete transfer of information. For
single–frame messages, the “message complete” condition occurs
at the end of the frame. For multi–frame (Fragmented) messages,
message complete occurs after the last frame is received and
stored. Since the hardware doesn’t recognize or handle
Fragmentation for transmit messages, the Tx message complete
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| PXAC37KFA/00,512 | 功能描述:IC XA MCU 16BIT 32K OTP 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:XA 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲(chǔ)器容量:40KB（20K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| PXAC37KFBD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
| PXAC37KFBD/00,157 | 功能描述:8位微控制器 -MCU 16B MCU 32K/1024 1 UART RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PXAG30KBA | 功能描述:16位微控制器 - MCU XA 16BIT 512R/2UART ROMLESS RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
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