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| 型號： | PXAC37KFA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-bit microcontroller family(16位微控制器系列) |
| 中文描述： | 16-BIT, OTPROM, 32 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 43/68頁 |
| 文件大?。?/td> | 344K |
| 代理商： | PXAC37KFA |
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Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
36
specification. Among other things, CAN Transport Layers permit
transmission of Messages which exceed the 8 byte Data limit
inherent to CAN Frames.
Fragmented Message
A lengthy message (in excess of 8 bytes) divided into data packets
and transmitted using a sequence of individual CAN Frames. The
specific ways that sequences of CAN Frames construct these
lengthy messages is defined within the context of a specific
CAN
T
ransport
L
ayer. The XA-C3 automatically re–assembles these
packets into the original, lengthy message in hardware and reports
(via interrupt) when the completed message is available as an
associated
Receive
Message Object
.
Message Buffer
A block of locations in XA Data memory where incoming (received)
messages are stored or where outgoing (transmit) messages are
staged.
MMR
Memory Mapped Register. An on–chip command/control/status
register whose address is mapped into XA Data memory space and
is accessed as Data memory by the XA processor.
Bus
Idle
SOF
1–bit
CAN.ID
11–bits
RTR
1–bit
IDE
1–bit
r0
1–bit
DLC
4–bit
CRC
15–bits
ACK
DEL
1–bit
Bus
Idle
SOF
1–bit
Base.ID
11– MSBs
SRR
1–bit
IDE
1–bit
r0
1–bit
DLC
4–bit
Extended.ID
18–LSBs
RTR
1–bit
r1
1–bit
EOF
7–bits
IFS
3–bits
Bus Idle
Standard
Extended
CRC
DEL
1–bit
ACK
1–bit
CRC
15–bits
ACK
DEL
1–bit
CRC
DEL
1–bit
ACK
1–bit
RTR
…
SRR
…
IDE
…
r1, r0
…
“
R
emote
S
ubstitute
ID E
xtension
r
eserved” bits
D
ata
L
ength
I
nter
F
rame
S
pace
T
ransmit
R
emote
R
equest
R
equest
DLC
…
IFS
…
C
ode (0, 1,
…
, 8)
SU01336
Data Field
(0, 1, ..., 8 Bytes)
0, 8, ..., 64-bits
Data Field
(0, 1, ..., 8 Bytes)
0, 8, ..., 64-bits
Figure 35. CAN Frame Formats
CTL/CAN Functionality of the XA-C3
Message Objects / Message Management
The XA-C3 allows the User to define up to 32 separate CTL/CAN
Message Objects.
Any of these 32 objects can be designated as either a Receive or
Transmit objects.
Any/all of the (up to 32) Receive Objects may be enabled to
hardware assemble multi frame “Fragmented” messages. For
Receive Objects so enabled,
CTL
/CAN hardware interrupts the
XA-C3 only at the completionof a multi–frame message which is
assembled in a contiguous fashion and stored in the Receive
message buffer associated with that object. At any given time,
XA-C3 may actively assemble (up to) 32 interleaved
CTL
messages.
Receive objects may also be used as circular CAN Frame buffers,
to store up to 28 CAN frames of 8 data bytes each, between CPU
interrupts.
Receive Objects, notenabled to hardware–assemble messages,
treat CAN2.0A/B Frames as complete (single–frame) messages
and are thus backwardcompatible with today’s FullCAN Message
Objects that store singleCAN frames.
XA-C3 supports most
CTL
/CAN protocols, i.e., Device.Net,
CANopen and OSEK.
Generally, hardware“Message–Management” on XA-C3 reduces
the
CTL
instruction bandwidth of today’s
CTL
message
processing from 80% to as low as 10%.
Acceptance Filtering
The XA-C3 provides extensive ID Screening/Filtering for 32
Message Objects. Each object has a full 30 bits of filter Match over
the
CTL
/CAN ID Fields as–well–as29 bits of Mask
…
per object.
That is, anycombination of (up to) 30 bits in the ID Fields may be
Masked out (“don’t care”) and/or Matched on an object–by–object
basis
Message Storage
Each of the 32 Message Objects has its own designated message
buffer space within the Data memory space addressed by the XA
processor. The size of each message buffer is independently User
specified up to a max of 256 bytes/object.
CTL
messages that
exceed the 256 byte/object limit can be accommodated with simple
software intervention.
The XA-C3 includes a 512 byte, on–board Message Buffer RAM
where some (or all) of the 32 (Rx/Tx) message buffers may reside.
Message Buffer RAM can be mapped anywhere in the 16 MByte
Data memory space addressed by the XA and can be extended
off–chip to a maximum of 8 KBytes. This off–chip expansion ability
can accommodate up to thirty–two, 256–byte message buffers.
Transmit Pre–Arbitration
Two (2) options are available to pre–arbitrate among pending
(currently enabled) transmit objects. A defaultoption selects and
transmits the object of highest–priority CAN arbitration ID (the same
criteria that arbitrates access to CAN bus itself). Transmit object
numberserves as a secondary tie–breaker for queuedtransmit
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| PXAC37KFA/00,512 | 功能描述:IC XA MCU 16BIT 32K OTP 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:XA 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲(chǔ)器容量:40KB（20K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| PXAC37KFBD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce |
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