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| 型號： | PSD702S5 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個可編程輸入/輸出，通用PLD的有66個輸入） |
| 文件頁數(shù)： | 70/104頁 |
| 文件大?。?/td> | 515K |
| 代理商： | PSD702S5 |
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PSD7XX Family
13-70
Supervisory
Function
(cont.)
The Power Monitor
(cont.)
The configuration options of the Voltage Comparator provided in the PSDsoft Design Tool
are:
J
Reference voltage source
J
Internal reference voltage level
J
Digital Sampler
J
Voltage Comparator disable
The internal Vtp level selections are shown in Table 38. Two V
CC
power supply options are
available: V
CC
± 5% or V
CC
± 10%. Depending on the selected V
CC
power supply option, a
fixed Vtp value is provided.
Vtp Range
Typical
Device
V
CC
Power
Min.
Max.
PSD7XXS5
5V ± 5%
5V ± 10%
4.47
4.08
4.61
4.29
4.75
4.50
Table 38. Internal Vtp Selection
Programmable Watchdog Timer
The WatchDog Timer consists of a retriggerable 9 bit counter. Once enabled, it starts
counting down from an initial value that is specified by the user in the PSDSoft Design Tool.
A WatchDog timeout is generated when the count reaches zero. The timeout output is
connected to the PPLD and the internal reset pulse generator.
The WatchDog Timer is enabled and controlled by the internal reset and the
PPLD outputs:
J
Internal Reset
The WatchDog Timer starts to count immediately after the trailing edge on the extended
reset (ERESET) pulse if it is enabled in the PSDsoft design tool.
J
PPLD Outputs
WDOG_EN
– If the WDOG_EN signal is defined in PSDabel, the Watchdog Timer
starts counting only after WDOG_EN generates a high pulse. This signal can be
defined in terms of the microcontroller address and the write signal. Writing to this
address by the microcontroller will enable the Watchdog Timer. The WDOG_EN signals
can be activated only after the extended reset (ERESET) expires.
WDOG_CLR
– This PPLD output signal re-loads and re-triggers the Watchdog
Timer. This signal is used to clear the WatchDog before a timeout is reached, and can
be defined in terms of the microcontroller address and the write signal. Writing to this
address by the microcontroller will clear the WatchDog.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD702S5-15L | 制造商:WSI 功能描述: |
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| PSD711S5-70L | 制造商:WSI 功能描述: |
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