參數(shù)資料
型號: PSD702S5
英文描述: Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯,4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備具有監(jiān)督職能(可編程邏輯,4K的位的SRAM,27余個可編程輸入/輸出,通用PLD的有66個輸入)
文件頁數(shù): 44/104頁
文件大?。?/td> 515K
代理商: PSD702S5
PSD7XX Family
13-44
I/O Ports
(cont.)
Control
Register Register Register
Setting
Setting
Direction
VM
Defined In
PSDabel
Defined In
PSDconfiguration
Mode
Setting
MCU I/O
Declare pins only
NA
0
1=output,
0=input
(Note 1)
NA
PLD I/O
Logic equations
NA
NA*
(Note 1)
NA
Data Port
(Port A,B)
NA
Specify bus type
NA
NA
NA
Address Out
(Port A,B)
Declare pins only
NA
1
1 (Note 1)
NA
Address In
(Port A,B,C)
Logic equation for
Input Micro
Cells
NA
NA
NA
NA
Peripheral I/O Logic equations
(Port A)
(PSEL0 & 1)
NA
NA
NA
PIO bit =1
Supervisory
Function
Logic equations
(WDOG_EN and
WDOG_CLR)
1. Specify clock
source
2. WatchDog
configuration
3. Reset output
4. Reference
voltage level
5. Standby voltage
configuration
NA
NA
NA
Table 23. Port Operating Mode Settings
*
NA – Not Applicable
NOTE 1: The direction of the Port A, B, C pins are controlled by the Direction Register ORed with the individual
output enable product term (.oe) from the GPLD AND array.
Port Operating Modes
(cont.)
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