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| 型號(hào)： | PSD702S5 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個(gè)可編程輸入/輸出，通用PLD的有66個(gè)輸入） |
| 文件頁(yè)數(shù)： | 19/104頁(yè) |
| 文件大?。?/td> | 515K |
| 代理商： | PSD702S5 |
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PSD7XX Family
13-19
PLDs
(cont.)
(INPUTS)
(4)
(16)
(3)
(1)
A[15:0]
PGR[3:0]
CNTRL[2:0], READ/WRITE
CONTROL SIGNALS
PDN
APD OUTPUT
POLARITY
BIT
POLARITY
BIT
POLARITY
BIT
ECS0
ECS1
ECS6
*
Figure 5. ECSPLD Logic Array
General PLD
The General PLD (GPLD) is used to implement system logic such as MCU loadable
counters, system mailboxes or handshaking protocols. In addition the GPLD can implement
random logic and state machine functions.
The GPLD has Output and Input Micro
Cells. The GPLD, Output and Input Micro
Cells
architectures appear in Figure 6 along with the Port. The Micro
Cells are configured using
the PSDsoft development system. Like the other PLDs, the GPLD has an AND array which
can generate up to 110 product terms, a maximum of nine product terms for each of the
twelve Micro
Cells.
The Input and Output Micro
Cells are connected to the PSD7XX internal data bus and
can be directly accessed by the microcontroller. This enables the MCU software to load
data into the Output Micro
Cells or read data from both the Input and Output Micro
Cells.
This feature allows efficient implementation of system logic and eliminates the need to
connect the data bus to the AND logic array as required in most standard PLD macrocell
architectures.
*
In 80C51XA mode, these address inputs are A[19:4].
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