參數(shù)資料
型號： PSD702S5
英文描述： Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個可編程輸入/輸出，通用PLD的有66個輸入）
文件頁數(shù)： 11/104頁
文件大小： 515K
代理商： PSD702S5
PSD7XX Family
13-11
Register Name
Port Port
A
01
Port Port
C
11
Other*
Description
B
00
D
10
Data In
Reads Port pin as input,
MCU I/O input mode
Selects mode between
MCU I/O or Address Out
Stores data for output to Port
pins, MCU I/O output mode
Configures Port pin as
input or output
Configures Port pin between
CMOS, Open Drain and
Slew rate
Reads Input Micro
Cell
Reads the status of the
output enable to the I/O
Port driver
Read – reads output of
Micro
Cells
(McellC, McellAB)
Write – loads Micro
cell
Flip-Flops
Power Management
Register 0
Power Management
Register 1
Page Register
8031/PIO Configuration
Register
Read only Supervisory
register. Indicates the
status and source of reset
and reference voltage level.
Write only. A write to the
register clears the reset
status bits in the Status
Register.
Read only. Indicates the
status of all Supervisory
I/O pins.
Read only. Indicates the
configuration of the
WatchDog Timer.
Contains WatchDog Timer
count bits 0–7.
Contains WatchDog Timer
count bit 8, the clock source
and reset pulse width.
Control
03
02
Data Out
05
04
13
12
Direction
07
06
15
14
Drive
09
08
17
16
Input Micro
Cell
Enable Out
0B
0D
0A
0C
19
1B
Output Micro
Cell
21
21
20
PMMR0
B1
PMMR1
B3
Page
VM
E1
E3
Status
D9
Reset-Clr
D7
Supv-Pins
DB
WD-Conf
D5
WD-Count
D1
WD-Misc
D3
Table 5A. Register Address Offset for 16-Bit Motorola Microcontrollers in
16-Bit Mode
PSD7XX
Register
Description
and Address
Offset
(cont.)
*
Other registers that are not part of the I/O ports.
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