參數(shù)資料
型號: PSD702S5
英文描述: Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯,4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備具有監(jiān)督職能(可編程邏輯,4K的位的SRAM,27余個(gè)可編程輸入/輸出,通用PLD的有66個(gè)輸入)
文件頁數(shù): 53/104頁
文件大?。?/td> 515K
代理商: PSD702S5
PSD7XX Family
13-53
I/O Ports
(cont.)
Port C – Functionality and Structure
Port C does not support Address Out mode and the Control Register is not required.
Port C can be configured to perform one or more of the following functions:
J
MCU I/O Mode
J
GPLD Output – McellC outputs can be connected to Port C pins
J
GPLD Input – via the eight Input Micro
Cells
J
Address In – Additional high address inputs using the Input Micro
Cells.
J
Open Drain – Port C pins can be configured in Open Drain Mode
J
Supervisory Function – Port C (PC1 – PC6) pins can be configured to perform the
Supervisory Function.
Pin PC7 may be configured as the WRH input in certain microcontroller interface designs.
Port D – Functionality and Structure
Port D has only three I/O pins, does not support Address Out mode, and no Control
Register is required. Port D can be configured to perform one or more of the following
functions:
J
MCU I/O Mode
J
ECSPLD Output – External chip select output
J
PLD Input – direct input to PLD, no Input Micro
Cells
J
Slew rate – pins can be set up for fast slew rate
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
J
PD0 – ALE, as address strobe input
J
PD1 – CLKIN, as clock input to the Micro
Cells Flip-Flops and APD counter
J
PD2 – CSI, as active low chip select input. A high input will disable
the PSD EPROM/SRAM.
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