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參數(shù)資料
| 型號(hào)： | PSD413A2F |
| 英文描述： | Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個(gè)可編程I/O,通用PLD有59個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備與快閃記憶體（可編程邏輯，16K的位的SRAM，35余個(gè)可編程輸入/輸出，通用PLD的有59個(gè)輸入） |
| 文件頁數(shù)： | 5/98頁 |
| 文件大?。?/td> | 365K |
| 代理商： | PSD413A2F |
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PSD413F Family
6-5
ADVANCE INFORMATION
The PSD413F contains two non-volatile memories (Boot and Flash) and a Standby SRAM.
The OTP Boot memory density is 8 Kbytes while the Flash memory density is 128 KBytes.
The OTP Boot memory allows for concurrent read and write operations during the time the
Flash memory is in the write or erase mode. The Flash memory includes the required
embedded write/erase operations and data polling capability. The DPLD and GPLD enable
efficient decoding to support the concurrent operation. The access time of the memories
includes the address latching and DPLD or GPLD decoding. The 16 Kbit Standby SRAM
may be used as an extension of the microcontroller SRAM and also to store backup infor-
mation that is necessary after a system power down or power failure. Standby power to the
SRAM is supplied by the Vstby pin. Switching between V
CC
and Vstby occurs automatically.
A four bit Page Register enables microcontrollers with limited address space easy access
to the I/O Section, Boot EPROM, Flash memory and SRAM memory. The Page Register
outputs are connected to all ZPLDs and can be used to page external devices as well as
the internal PSD413F functional sections.
A Power Management Unit (PMU) in the PSD413F enables the user to control the
power consumption on selected functional blocks based on system requirements. For
microcontrollers that cannot generate a Chip Select input (CSI) to the peripheral device,
the PMU includes an Automatic Power Down unit (APD) that will turn off the PSD413F
(to standby mode) based on inactivity of the ALE. The polarity of ALE inactivity can be
configured by the user.
The PSD413F family is supported by the WSI PSDsoft development system (see Figure 2)
which runs under MS-Windows
or Windows 95
on the PC. Design entry is done using
PSDabel which creates a minimized logic implementation. PSDabel also provides logic
simulation. The PSD413F desired configuration is entered using a simple Windows based
menu. The PSDcompiler, which consists of a Fitter and an Address Translator, generates an
object file from the PSDabel and configuration files. The object file can be down loaded to a
programmer (MagicPro
III or third party).
General
Description
(Cont.)
相關(guān)PDF資料 |
PDF描述 |
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| PSD4235G2(中文) | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片) |
| PSD4235G2 | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片) |
| PSD4235G2 | FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY) |
| PSD4235G2V | -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-254AA package; A JANSR2N7426 with Standard Packaging |
| PSD4235G1-B-12J | Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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