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| 型號： | PSD413A2F |
| 英文描述： | Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個可編程I/O,通用PLD有59個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設備與快閃記憶體（可編程邏輯，16K的位的SRAM，35余個可編程輸入/輸出，通用PLD的有59個輸入） |
| 文件頁數(shù)： | 39/98頁 |
| 文件大?。?/td> | 365K |
| 代理商： | PSD413A2F |
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PSD413F Family
6-39
ADVANCE INFORMATION
PSD413F Interface To Non-Multiplexed Bus
Figure 21 shows a PSD413F interfacing to a microcontroller with a non-multiplexed
address/data bus. The address bus is connected to the ADIO Port, and the data bus is
connected to Port C. There is no need for the ADIO Port to latch the address internally, but
the user is offered the option to do so in the PSD413F PSDsoft Software. The data Ports
are in tri-state mode when the PSD413F is not accessed by the microcontroller.
Optional Features
The PSD413F provides two optional features to add flexibility to the Bus Interface:
1. Address In
Port A can be configured as high order address inputs to the ZPLD for EPROM or other
decoding. Inputs are latched by ALE/AS if Multiplexed Bus is selected. Other Ports can
be configured as address input ports for the ZPLD. These inputs should not be used for
Boot EPROM or Flash memory decoding and are not latched internally.
2. Address Out
For multiplexed bus only. Latched address lines A0-A15 are available on
Port A, B, C or D.
Details on the optional features are described in the I/O Port section.
Bus
Interface
(Cont.)
Bus Interface Examples
The next two figures show the PSD413F interfacing with two popular microcontrollers.
The examples show only the basic bus connections; some of the pin names on the
PSD413F parts change to reflect the actual pin functions.
Figure 22 shows the interface to the 80C31. The 80C31 has a 16 bit address bus and an
8-bit data bus. The lower address byte is multiplexed with the data bus. The RD and WR
signals are used for accessing the data memory and the PSEN signal is for reading
program memory. The ALE signal is active high and is used to latch the address internally.
Port C provides latched address outputs A[7:0]. Ports A, B, D, and E (PE2-PE7) can be
configured to perform other functions. The RSTOUT reset to the 80C31 is generated by the
ZPLD from the RESET input. This configuration eliminates any reset race condition
between the 80C31 and the PSD413F.
Figure 23 shows the 68HC11 interface, which is similar to the 80C31 except the PSD413F
generates internal RD and WR from the 68HC11’s E and R/W signals.
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| PSD4235G2 | FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY) |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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