參數(shù)資料
型號(hào)： PSB3186
英文描述： The IRAC1150-D2 Control Board is designed to demonstrate the performance of the IR1150S control IC in a continuous conduction mode boost converter for PFC.; A IRAC1150-D2 with Standard Packaging
中文描述： 3.3伏ISDN用戶終端訪問(wèn)控制器eXtended擴(kuò)展
文件頁(yè)數(shù)： 89/200頁(yè)
文件大?。?/td> 2959K
代理商： PSB3186
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
Data Sheet
89
2003-01-30
Since a
double last-look criterion
is implemented the receiver is able to receive the
MON slot data at least twice (in two consecutive frames), the receiver waits for the
acknowledge of the reception of two identical bytes in two successive frames.
To control this handshake procedure a collision detection mechanism is implemented
in the transmitter. This is done by making a
collision check
per bit on the transmitted
MONITOR data and the MX bit.
Monitor data will be transmitted repeatedly until its reception is acknowledged or the
transmission time-out timer expires.
Two frames with the MX bit in the inactive state indicates the
end of a message
(EOM).
Transmission and reception of monitor messages can be performed simultaneously.
This feature is used by the ISAC-SX TE to send back the response before the
transmission from the controller is completed (the ISAC-SX TE does not wait for EOM
from controller).
3.7.3.2
In case the ISAC-SX TE does not detect identical monitor messages in two successive
frames, transmission is not aborted. Instead the ISAC-SX TE will wait until two identical
bytes are received in succession.
A transmission is aborted of the ISAC-SX TE if
an error in the MR handshaking occurs
a collision on the IOM-2 bus of the MONITOR data or MX bit occurs
the transmission time-out timer expires
A reception is aborted by the device if
an error in the MX handshaking occurs or
an abort request from the opposite device occurs
Error Treatment
MX/MR Treatment in Error Case
In the master mode the MX/MR bits are under control of the microcontroller through MXC
or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt,
respectively.
In the slave mode the MX/MR bits are under control of the device. An abort is always
indicated by setting the MX/MR bit inactive for two or more IOM-2 frames. The controller
must react with EOM.
Figure 49
shows an example for an abort requested by the receiver,
Figure 50
shows
an example for an abort requested by the transmitter and
Figure 51
shows an example
for a successful transmission.
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