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參數(shù)資料
| 型號： | PSB3186 |
| 英文描述： | The IRAC1150-D2 Control Board is designed to demonstrate the performance of the IR1150S control IC in a continuous conduction mode boost converter for PFC.; A IRAC1150-D2 with Standard Packaging |
| 中文描述： | 3.3伏ISDN用戶終端訪問控制器eXtended擴展 |
| 文件頁數(shù)： | 72/200頁 |
| 文件大?。?/td> | 2959K |
| 代理商： | PSB3186 |
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
Data Sheet
72
2003-01-30
3.7.1.1
With its four controller data access registers (CDA10, CDA11, CDA20, CDA21) the
ISAC-SX TE IOM-2 handler provides a very flexible solution for the host access to up to
32 IOM-2 timeslots. However, in the normal mode (DCL output = 1.536 MHz) 12
timeslots are supported. Only if the transceiver is disabled (DIS_TR = ’1’) and external
clocks are provided, up to 32 timeslots (DCL input = 4.096 MHz) can be used.
The functional unit CDA (controller data access) allows with its control and configuration
registers
looping of up to four independent PCM channels from DU to DD or vice versa over the
four CDA registers
shifting of two independent PCM channels to another two independent PCM channels
on both data ports (DU, DD). Between reading and writing the data can be
manipulated (processed with an algorithm) by the microcontroller. If this is not the
case a switching function is performed
monitoring of up to four timeslots on the IOM-2 interface simultaneously
microcontroller read and write access to each PCM timeslot
The access principle which is identical for the two channel register pairs CDA10/11 and
CDA20/21 is illustrated in
Figure 38
. Each of the index variables x,y used in the following
description can be 1 or 2 for x and 0 or 1 for y. The prefix ’CDA_’ from the register names
has been omitted for simplification.
To each of the four CDAxy data registers a TSDPxy register is assigned by which the
timeslot and the data port can be determined. With the TSS (Timeslot Selection) bits a
timeslot from 0...31 can be selected. With the DPS (Data Port Selection) bit the output
of the CDAxy register can be assigned to DU or DD, respectively. The timeslot and data
port for the output of CDAxy is always defined by its own TSDPxy register. The input of
CDAxy depends on the SWAP bit in the control registers CRx.
If the SWAP bit = ’0’ (swap is disabled) the timeslot and data port for the input and
output of the CDAxy register is defined by its own TSDPxy register.
If the SWAP bit = ’1’ (swap is enabled) the input port and timeslot of the CDAx0 is
defined by the TSDP register of CDAx1 and the input port and timeslot of CDAx1 is
defined by the TSDP register of CDAx0. The input definition for timeslot and data port
CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output
timeslots are not affected by SWAP.
The input and output of every CDAxy register can be enabled or disabled by setting the
corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is
disabled the output value in the register is retained.
Usually one input and one output of a functional unit (transceiver, HDLC controller, CDA
register) is programmed to a timeslot on IOM-2 (e.g. for B-channel transmission in
upstream direction the HDLC controller writes data onto IOM and the transceiver reads
data from IOM). For monitoring data in such cases a CDA register is programmed as
Controller Data Access (CDA)
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