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參數(shù)資料
| 型號(hào)： | PSB3186 |
| 英文描述： | The IRAC1150-D2 Control Board is designed to demonstrate the performance of the IR1150S control IC in a continuous conduction mode boost converter for PFC.; A IRAC1150-D2 with Standard Packaging |
| 中文描述： | 3.3伏ISDN用戶終端訪問(wèn)控制器eXtended擴(kuò)展 |
| 文件頁(yè)數(shù)： | 50/200頁(yè) |
| 文件大?。?/td> | 2959K |
| 代理商： | PSB3186 |
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
Data Sheet
50
2003-01-30
3.3.6.2
Synchronization problems can occur on a S-Bus that is not terminated properly.
Therefore, it is recommended to change the resistor values in the receive path. The sum
of both resistors is increased from 10 k (1.8 + 8.2) to e.g. 34 k (6.8 + 27) for either
receiver line. This change is possible but not necessary for a S-Bus that is terminated
properly.
S-Transceiver Synchronization
Figure 25
External Circuitry for Symmetrical Receivers
Note: Lower or higher values than 34 k may be used as well, however for values above
34 k the additional delay must be compensated by setting TR_CONF2.PDS=1
(compensates 260 ns) so the allowed input phase delay is not violated.
3.3.7
The S/T transmitter is shifted by two S/T bits minus 7 oscillator periods (plus analog
delay plus delay of the external circuitry) with respect to the received frame. To
compensate additional delay introduced into the receive and transmit path by the
external circuit the delay of the transmit data can be reduced by another two oscillator
periods (2 x 130 ns). Therefore PDS of the TR_CONF2 register must be programmed to
’1’. This delay compensation might be necessary in order to comply with the "total phase
deviation input to output" requirement of ITU-T recommendation I.430 which specifies a
phase deviation in the range of – 7% to + 15% of a bit period.
S/T Interface Delay Compensation
3.3.8
If MODE1.CFS is set to ’0’, the clocks are also provided in power down state, whereas
if CFS is set to ’1’ only the analog level detector is active in power down state. All clocks,
including the IOM-2 interface, are stopped (DD, DU are ’high’, DCL and BCL are ’low’).
Level Detection Power Down
Note: Capacitors (up to 10 pF) are optional for noise reduction.
21150_33
1:1
S Bus
SR2
SR1
GND
V
DD
R1
R2
R1
R2
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