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參數(shù)資料
| 型號： | PSB3186 |
| 英文描述： | The IRAC1150-D2 Control Board is designed to demonstrate the performance of the IR1150S control IC in a continuous conduction mode boost converter for PFC.; A IRAC1150-D2 with Standard Packaging |
| 中文描述： | 3.3伏ISDN用戶終端訪問控制器eXtended擴展 |
| 文件頁數(shù)： | 104/200頁 |
| 文件大?。?/td> | 2959K |
| 代理商： | PSB3186 |
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ISAC-SX TE
PSB 3186
Description of Functional Blocks
Data Sheet
104
2003-01-30
3.8.2
Data Reception
3.8.2.1
The cyclic receive FIFO buffer with a length of 64 byte has a variable FIFO block size
(threshold) of 4, 8, 16 or 32 bytes which can be selected by setting the corresponding
RFBS bits in the EXMD register. The variable block size allows an optimized HDLC
processing concerning frame length, I/O throughput and interrupt load.
The transfer protocol between HDLC FIFO and microcontroller is block oriented with the
microcontroller as master. The control of the data transfer between the CPU and the
ISAC-SX TE is handled via interrupts (ISAC-SX TE
ISAC-SX TE).
There are three different interrupt indications in the ISTAD registes concerned with the
reception of data:
–
RPF
(
R
eceive
P
ool
F
ull) interrupt, indicating that a data block of the selected length
(EXMD.RFBS) can be read from RFIFOD. The message which is currently received
exceeds the block size so further blocks will be received to complete the message.
–
RME
(
R
eceive
M
essage
E
nd) interrupt, indicating that the reception of one message
is completed, i.e. either
a short message is received
(message length
the defined block size (EXMD.RFBS)) or
the last part of a long message is received
(message length
the defined block size (EXMD.RFBS))
and is stored in the RFIFOx.
–
RFO
(
R
eceive
F
rame
O
verflow) interrupt, indicating that a complete frame could not
be stored in RFIFOD and is therefore lost as the RFIFOD is occupied. This occurs if
the host fails to respond quickly enough to RPF/RME interrupts since previous data
was not read by the host.
Structure and Control of the Receive FIFO
Host) and commands (Host
There are two control commands that are used with the reception of data:
–
RMC
(
R
eceive
M
essage
C
omplete) command, telling the ISAC-SX TE that a data
block has been read from the RFIFOD and the corresponding FIFO space can be
released for new receive data.
–
RRES
(
R
eceiver
R
eset) command, resetting the HDLC receiver and clearing the
receive FIFO of any data (e.g. used before start of reception). It has to be used after
a change of the message transfer mode. Pending interrupt indications of the receiver
are not cleared by RRES, but have to be cleared by reading these interrupts.
Note: The significant interrupts and commands are underlined as only these are
commonly used during a normal reception sequence.
The following description of the receive FIFO operation is illustrated in
Figure 60
for a
RFIFOD block size (threshold) of 16 and 32 bytes.
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