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參數(shù)資料
| 型號： | PPC440SPE |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440SPe Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440SPe |
| 文件頁數(shù)： | 68/80頁 |
| 文件大?。?/td> | 572K |
| 代理商： | PPC440SPE |
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PowerPC 440SPe Embedded Processor
68
AMCC Proprietary
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
EMCTxEn
EMCTxErr
Internal Peripheral Interface
IIC0SClk
IIC0SDA
IIC1SClk
IIC1SDA
UARTSerClk
UART0_Rx
UART0_Tx
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RI
UART0_RTS
UART1_Rx
UART1_Tx
UART1_DSR/CTS
UART1_DTR/RTS
UART2_Rx
UART2_Tx
Interrupts Interface
IRQ0:15
JTAG Interface
TDI
TMS
TDO
TCK
TRST
System Interface
Halt
GPIO00:31
SysClk
SysErr
SysReset
HISRRst
TESTEN
TmrClk
Trace Interface
TrcClk
TRCBS0:2
TrcES0:4
TrcTS0:6
na
na
na
na
15
15
2
2
19.1
19.1
8.7
8.7
EMCTxClk
EMCTxClk
n/a
-
n/a
-
n/a
-
n/a
-
-
-
n/a
-
n/a
n/a
-
n/a
-
n/a
-
n/a
-
-
-
n/a
-
n/a
n/a
-
n/a
-
n/a
n/a
-
n/a
n/a
n/a
n/a
-
n/a
-
n/a
n/a
-
n/a
n/a
n/a
15.3
15.3
15.3
15.3
19.1
-
19.1
19.1
19.1
19.1
19.1
-
19.1
19.1
19.1
19.1
19.1
19.1
19.1
10.2
10.2
10.2
10.2
8.7
-
8.7
8.7
8.7
8.7
8.7
-
8.7
8.7
8.7
8.7
8.7
8.7
8.7
IIC0SClk
IIC0SClk
UARTSerClk
UARTSerClk
async
async
async
async
async
async
UARTSerClk
UARTSerClk
async
async
UARTSerClk
UARTSerClk
n/a
n/a
n/a
-
n/a
n/a
-
n/a
n/a
-
n/a
-
n/a
n/a
-
n/a
-
n/a
n/a
-
n/a
-
-
-
-
-
n/a
n/a
async
-
-
-
-
na
na
-
na
na
na
na
-
na
na
na
na
19.1
na
na
na
na
8.7
na
na
async
async
async
async
async
na
-
-
na
-
-
-
-
-
-
-
-
n/a
-
n/a
-
-
-
n/a
n/a
n/a
-
n/a
-
-
-
n/a
n/a
n/a
19.1
n/a
19.1
n/a
19.1
n/a
n/a
n/a
8.7
n/a
8.7
n/a
8.7
n/a
n/a
async
async
na
async
async
async
async
na
n/a
-
-
-
-
n/a
-
-
-
-
n/a
-
-
-
n/a
-
-
-
-
-
-
-
-
-
-
-
19.1
19.1
19.1
19.1
8.7
8.7
8.7
8.7
Table 14. I/O Specifications—All Speeds (Sheet 2 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2.
PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz
and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time
requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
3. These are DDR signals that can change on both the positive and negative clock transitions.
Signal
Input (ns)
Output (ns)
Output Current (mA)
I/O H
(minimum)
Clock
Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I/O L
(minimum)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440SPE-3GA533C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-3GA667C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-AGB533C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-AGB667C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-ANB533C | PowerPC 440SPe Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440SPE-3GA533C | 制造商:AppliedMicro 功能描述: |
| PPC440SPE-3GA667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
| PPC440SPE-3NA533C | 制造商:AppliedMicro 功能描述: |
| PPC440SPE-AGB533C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
| PPC440SPE-AGB667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
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