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參數(shù)資料
| 型號(hào)： | PPC440SPE |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440SPe Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440SPe |
| 文件頁(yè)數(shù)： | 54/80頁(yè) |
| 文件大?。?/td> | 572K |
| 代理商： | PPC440SPE |
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PowerPC 440SPe Embedded Processor
54
AMCC Proprietary
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
External Slave Peripheral Interface - EBC
PerAddr00:26
Peripheral address bus.
Note:
PerAddr00 is the most significant bit (msb).
O
3.3V LVTTL
1
PerBE0:1
External peripheral data bus byte enable.
O
3.3V LVTTL
1
PerBLast
Used by the peripheral controller to indicates the last
transfer of a memory access.
O
3.3V LVTTL
PerCS0:2
External peripheral device select.
O
3.3V LVTTL
PerData00:15
Peripheral data bus.
Note:
PerData0 is the most significant bit (msb).
I/O
3.3V LVTTL
1
PerOE
Used by peripheral controller or DMA controller
depending upon the type of transfer involved. When the
PPC440SPe is the bus master, it enables the selected
device to drive the bus.
O
3.3V LVTTL
PerPar0:1
External peripheral data bus byte parity.
I/O
3.3V LVTTL
1
PerReady
Used by a peripheral slave to indicate it is ready to
transfer data.
I
3.3V LVTTL
PerR/W
The peripheral controller set this signal to High for a
Read from external memory, and to Low for a Write.
O
3.3V LVTTL
1
PerWE
Write Enable.
O
3.3V LVTTL
PerClk
Peripheral clock used by synchronous peripheral slaves.
O
3.3V LVTTL
PerErr
External error used as an input to record external slave
peripheral errors.
I
3.3V LVTTL
1, 5
IIC Peripheral Interface
IIC0SClk
IIC0 Serial Clock.
I/O
3.3V IIC
1, 2
IIC0SDA
IIC0 Serial Data.
I/O
3.3V IIC
1, 2
IIC1SClk
IIC1 Serial Clock.
I/O
3.3V IIC
1, 2
IIC1SDA
IIC1 Serial Data.
I/O
3.3V IIC
1, 2
Table 6. Signal Functional Description (Sheet 5 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440SPE-3GA533C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-3GA667C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-AGB533C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-AGB667C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-ANB533C | PowerPC 440SPe Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440SPE-3GA533C | 制造商:AppliedMicro 功能描述: |
| PPC440SPE-3GA667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
| PPC440SPE-3NA533C | 制造商:AppliedMicro 功能描述: |
| PPC440SPE-AGB533C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
| PPC440SPE-AGB667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
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