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參數(shù)資料
| 型號： | PPC440SPE |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440SPe Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440SPe |
| 文件頁數(shù)： | 14/80頁 |
| 文件大?。?/td> | 572K |
| 代理商： | PPC440SPE |
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PowerPC 440SPe Embedded Processor
14
AMCC Proprietary
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
For more information about the RAID 6 implementation, description, and configuration of the acceleration
hardware, refer to the following AMCC documents:
PowerPC 440SP/440SPe RAID Support Application Note
PowerPC 440SPe RAID Addendum to the User’s Manual
XOR/DMA2 Controller
The XOR/DMA2 controller performs the XOR functions needed to support RAID 5 applications including parity
generation and check functions used across data stripes in a RAID 5 system.
Computes a bit-wise XOR on up to 16 data streams with result stored in designated target
Performs XOR check on up to 16 data streams
Driven by a linked list Command Block structure specifying control information, source operands, target
operand, status information, and link
Source and target streams may reside anywhere in PLB address space.
Provides completion status per Command Block to be handled by software at a later time
96-byte and 160-byte Command Block formats are supported
No memory alignment restrictions on operands or target
Internal register arrays and data buffers are parity protected
Can be used as a DMA controller (DMA2) with single source and target addresses
PLB Master interface
PLB Slave port used as control interface for reading and writing control and status information
Serial Port
The serial port is compatible with the NS
16570 UART interface.
Features include:
One 8-pin, one 4-pin, and one 2-pin interfaces are provided
Selectable internal or external serial clock to allow wide range of baud rates
Register compatibility with 16750 register set
Complete status reporting capability
Fully programmable serial-interface characteristics
IIC Bus Interface
Features include:
Two IIC interfaces provided
Support for Philips
Semiconductors I
2
C Specification, dated 1995
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Supports fixed V
DD
IIC interface
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Full management of all IIC bus protocols
Programmable error recovery
Port 0 supports serial Bootstrap ROM with default override parameters at initialization
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440SPE-3GA533C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-3GA667C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-AGB533C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-AGB667C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-ANB533C | PowerPC 440SPe Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440SPE-3GA533C | 制造商:AppliedMicro 功能描述: |
| PPC440SPE-3GA667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
| PPC440SPE-3NA533C | 制造商:AppliedMicro 功能描述: |
| PPC440SPE-AGB533C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
| PPC440SPE-AGB667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
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