參數(shù)資料
型號(hào)： PPC440SPE
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 440SPe Embedded Processor
中文描述： 嵌入式處理器的PowerPC 440SPe
文件頁(yè)數(shù)： 12/80頁(yè)
文件大小： 572K
代理商： PPC440SPE
PowerPC 440SPe Embedded Processor
12
AMCC Proprietary
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
PCI-X initialization sequence support (frequency & mode determination)
Support for unexpected split completions
Outbound transaction split discard timers
Vital Product Data (VPD) support
PCI-X to PCI-Express opaque bridge
DDR1/DDR2 SDRAM Memory Controller
The DDR2 SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, and other discrete
devices. Global memory timings, address and bank sizes, and memory addressing modes are programmable. The
DDR2 SDRAM controller interfaces to the PLB through a Memory Queue (MQ) function that includes six high-
speed 1KB FIFO buffers.
Features include:
Registered and non-registered industry standard DIMMs
DDR2 400/667 support
64-and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)
5.32GB/s peak bandwidth for the 64-bit interface
2.66GB/s peak bandwidth for the 32-bit interface
Four chip (bank) select signals supporting 4 external banks
CAS latencies of 2, 3, 4, 5, 6, and 7 supported
Page mode accesses (up to 32 open pages) with configurable paging policy
Look-ahead request queue with programmable depth of four commands.
Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current
bank)
Up to 16GB in four external banks
Up to 6 MemClkout signals for high loading unbuffered DIMMS
.
Programmable address mapping and timing
Hardware and software initiated self-refresh
Sync DRAM configuration by means of mode register and extended mode register set commands
Power management (self-refresh, suspend, sleep)
Low Latency & High Bandwidth PLB ports
Selectable PLB read response (immediate or deferred)
Programmable Low Latency & High Bandwidth arbitration schemes
High Bandwidth port has four 1KB read buffers and two 1KB write buffers
Low Latency port has four 128B read buffers and two 128B write buffers
External Peripheral Bus Controller (EBC)
Features include:
Support Boot ROM on Bank 0; programmable size 2, 4, 8,16 MB
Up to three ROM, EPROM, SRAM, Flash memory, and slave peripherals supported
Burst and non-burst devices
16 or 8-bit data bus
27-bit address, 128MB address space for Banks 1 & 2
Peripheral Device pacing with external “Ready”
Latch data on Ready, synchronous or asynchronous
Programmable access timing per device
– 256 Wait States for non-burst
– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
– Programmable CSon, CSoff relative to address
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
Programmable address mapping
相關(guān)PDF資料
PDF描述
PPC440SPE-3GA533C PowerPC 440SPe Embedded Processor
PPC440SPE-3GA667C PowerPC 440SPe Embedded Processor
PPC440SPE-AGB533C PowerPC 440SPe Embedded Processor
PPC440SPE-AGB667C PowerPC 440SPe Embedded Processor
PPC440SPE-ANB533C PowerPC 440SPe Embedded Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC440SPE-3GA533C 制造商:AppliedMicro 功能描述:
PPC440SPE-3GA667C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor
PPC440SPE-3NA533C 制造商:AppliedMicro 功能描述:
PPC440SPE-AGB533C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor
PPC440SPE-AGB667C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor
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