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參數(shù)資料
| 型號： | PPC440SPE |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440SPe Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440SPe |
| 文件頁數(shù)： | 51/80頁 |
| 文件大?。?/td> | 572K |
| 代理商： | PPC440SPE |
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PowerPC 440SPe Embedded Processor
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
AMCC Proprietary
51
PCIX0Clk
Input PCI & PCI-X Clock.
Note:
If the PCI-X interface is not being used, drive this
pin with a 3.3V clock signal at a frequency
between 1 and 66MHz
I
3.3V PCI
PCIX0DevSel
Indicates the driving device has decoded its address as
the target of the current access.
I/O
3.3V PCI
4
PCIX0ECC5:2
ECC check bits 5–2. All ECC bits are valid only for PCIX
DDR mode 2.
Note:
See PCIXPar for ECC0.
See PCIXAck64 for ECC1.
See PCIXReq64 for ECC6.
See PCIXPar64 for ECC7.
I/O
3.3V PCI or
1.5V PCI for
mode 2
PCIX0Frame
Driven by the current master to indicate beginning and
duration of an access.
I/O
3.3V PCI
4
PCIX0Gnt0
PCIX0Gnt1:3
Indicates that the specified agent is granted access to
the PCI-X bus. When Arbitration is internal to the
PPC440SPe, all GRANTS Gnt0:3 are outputs. When
arbitration is external, only Gnt 0 is used as an Input.
I/O
O
3.3V PCI
4
PCIX0IDSel
Used as a chip select during configuration read and
write transactions. If the PCI-X is a Host, during
Configuration the ISDSEL is an Output that duplicates
the AD17. The ISDSEL is always 3.3V even in Mode 2
DDR
I/O
3.3V PCI
5
PCIX0INTA
Level sensitive PCI interrupt.
O
3.3V PCI
PCIX0IRDY
Indicates initiating agent’s ability to complete the current
data phase of the transaction.
I/O
3.3V PCI
4
PCIX0M66En
Capable of 66MHz operation.
I
3.3V PCI or
1.5V PCI for
mode 2
PCIX0Par/PCIX0ECC0
Even parity indicator or ECC0.
Normally used to indicate even parity across
PCIAD31:00 and BE3:0.
Used as ECC0 for PCIX0 mode 2.
I/O
3.3V PCI or
1.5V PCI for
mode 2
PCIX0Par64/PCIX0ECC7
Even parity indicator or ECC7.
Normally used to indicate even parity across
PCIXAD63:32 and BE7:4 for PCIX0
or
Used as ECC7 for PCIX0 mode 2.
I/O
3.3V PCI or
1.5V PCI for
mode 2
PCIX0PErr
Reports data parity errors during all PCI transactions
except a Special Cycle.
I/O
3.3V PCI
4
PCIX0Req0
PCIX0Req1:3
An indication to the PCI-X arbiter that the specified
agent wishes to use the bus.
When Arbitration is internal to the PPC440SPe, all
REQS Req0:3 are Inputs. When arbitration is external,
only Req 0 is used as an output.
I/O
I
3.3V PCI
4
Table 6. Signal Functional Description (Sheet 2 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關PDF資料 |
PDF描述 |
|---|---|
| PPC440SPE-3GA533C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-3GA667C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-AGB533C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-AGB667C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-ANB533C | PowerPC 440SPe Embedded Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440SPE-3GA533C | 制造商:AppliedMicro 功能描述: |
| PPC440SPE-3GA667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
| PPC440SPE-3NA533C | 制造商:AppliedMicro 功能描述: |
| PPC440SPE-AGB533C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
| PPC440SPE-AGB667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
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