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PowerPC 440SPe Embedded Processor
78
AMCC Proprietary
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
Document Revision History
Revision
Date
Description
1.23
Sept 21, 2006
Updated Recommended DC Operating Conditions table.
1.22
Sept 12, 2006
Updated Processor Clock values in Clocking Specifications table.
1.21
June 27, 2006
Updated Recommended DC Op Conditions and Signal Functional Description tables for PCI-X
DDR mode 2.
1.20
June 14, 2006
Updated signal lists. Corrected reference to PCIX0Cap in Signal Functional Description table.
Added reference to Note 6 for UART0_CTS register in Signal Functional Description table.
1.19
May 23, 2006
Fixed doc issue for PEROE signal in Signal Functional Description table. Fixed doc issue for
UARTSerClk signal throughout document. Fixed doc issue for PSRO1 signal in Signal Functional
Description table. Updated Clocking Specifications table and Serial Bootstrap ROM paragraph.
1.18
May 1, 2006
Updated ordering and PVR information, and core package graphic in Figure 3. Added RAID
acceleration section to Features, Description, and functional details sections.
1.17
April 6, 2006
Additional update to ordering and PVR information. GJG
1.16
March 8, 2006
Updated ordering and PVR information, part number list, and package diagram. GJG
1.15
March 7, 2006
Removed DMA statement from Serial Port feature statement. Removed reference to notes from
PERBLAST entry in signal functional description table. GJG
1.14
March 6, 2006
Updated description of On-Chip SRAM/L2 Cache in Introduction. GJG
1.13
January 9, 2006
Updated Signal Function Description table per JB, updated mailing address and copyright date in
disclaimer. GJG
1.12
November 15, 2005
Clarified information about DDR SDRAM I/O specifications. GJG
1.11
October 26, 2005
Corrected upper limit of allowable case temperature, documented reserved signal pins, added
bookmarks for signal lists. GJG
1.10
October 17, 2005
Restored multiplexed signal information to the “Signals Listed Alphabetically” table. Applied
corrections to the table from GB. GJG
1.09
July 12, 2005
Updated leakage current info, case temp range, DDR SDRAM Signal Termination graphic. GJG
1.08
May 23, 2005
Update Write timing diagrams. GJG
1.07
May 20, 2005
Updated system memory address map. Corrected functional block diagram. GJG
1.06
Mar 10, 2005
Removed text for unsupported COLA component. GJG
1.05
Feb 15, 2005
Removed references to unsupported COLA serial interface. Reformatted LOF, LOT to comply with
AMCC style. GJG
1.04
Dec 21, 2004
Update max case temp in Recommended DC Op Conditions table to match Ordering and PVR
Information table. GJG
1.03
Dec 20, 2004
Update Ordering and PVR info, PCI Express features info, DDR SDRAM read data path and read
cycle timing example, memory map. GJG
1.02
Sept 21, 2004
PCI-Express Rx Tx pin assignment changes. GJG
1.01
Sept 13, 2004
Converted to AMCC format, corrected tables, graphics as needed. GJG
0.5
Sept 10, 2004
Renamed 440SPe, added Mux table, VDDA 2.5V (IN PROGRESS)
0.4
Aug 02, 2004
Miscellaneous technical additions, PN and corrections from Support.
0.3
July 18, 2004
Correct TOC, LOF, LOT, broken cross-references.
0.2
June 25, 2004
Add alphabetic list, update Sys Mem address map.
0.1
June 18, 2004
Create initial data sheet.