參數(shù)資料
型號： PPC440SPE-ANB667C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 440SPe Embedded Processor
中文描述： 32-BIT, 667 MHz, RISC PROCESSOR, PBGA675
封裝： 27 X 27 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, FCBGA-675
文件頁數(shù)： 56/80頁
文件大?。?/td> 572K
代理商： PPC440SPE-ANB667C
PowerPC 440SPe Embedded Processor
56
AMCC Proprietary
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
HISRRst
Hardware initiated system reset with an initial SDRAM
self-refresh phase to save data in Memory.
I
3.3V LVTTL
1, 2
TESTEN
Test Enable.
I
3.3V LVTTL
3
TMR_CLK
Processor timer external input clock.
I
3.3V LVTTL
JTAG Interface
TCK
Test Clock.
I
3.3V LVTTL
1
TDI
Test Data In.
I
3.3V LVTTL
w/pull-down
4
TDO
Test Data Out.
O
3.3V LVTTL
TMS
Test Mode Select.
I
3.3V LVTTL
with pull-up
1
TRST
Test Reset. During chip power-up, this signal must be
low from the start of VDD ramp-up until at least 16
SysClk cycles after VDD is stable in order to initialize the
JTAG controller.
I
3.3V LVTTL
with pull-up
5
Trace Interface
TrcClk
Trace data capture clock, runs at 1/4 the frequency of
the processor.
O
3.3V LVTTL
TRCBS0:2
Trace branch execution status.
O
3.3V LVTTL
TrcES0:4
Trace Execution Status is presented every fourth
processor clock cycle.
O
3.3V LVTTL
TrcTS0:6
Additional information on trace execution and branch
status.
O
3.3V LVTTL
Tests
SCANOUT[00][07:08] [14:21] [25]
Test scan out
Manufacturing test signals: No need for termination
n/a
Power
PCIE0:2AV25
2.5V supply voltage for the serial link of the PCI Express
I
PCIE_PLLVDD2
2.5V supply voltage for the PCI Express Reference
clock Input receiver in front of the PLL
I
PCIE_PLLVDDA
Analog 2.5V filtered supply voltage A for the PLL of the
PCI Express
I
PCIE_PLLVDDB
Analog 2.5V filtered supply voltage B for the PLL of the
PCI Express
I
PCIE_PLLGNDA
GNDA for the PLL of the PCI Express
I
PCIE_PLLGNDB
GNDB for the PLL of the PCI Express
I
PCIX0PLLG
Ground for the PCI-X0 PLL
n/a
n/a
PCIX0PLLV
Analog 1.5V Filtered Supply voltages input for PCI-X0
A separate filter for all analog voltages is recommended.
I
n/a
Table 6. Signal Functional Description (Sheet 7 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC440SPE-ANB800C 制造商:AppliedMicro 功能描述:MPU 440SPe RISC 16-Bit 0.13mm 800MHz 1.5V/3.3V 675-Pin FCBGA Tray 制造商:Applied Micro Circuits Corporation 功能描述:MPU 440SPe RISC 16-Bit 0.13mm 800MHz 1.5V/3.3V 675-Pin FCBGA Tray
PPC440SPE-RGB533C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor
PPC440SPE-RGB667C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor
PPC440SPE-RNB533C 制造商:AppliedMicro 功能描述:MPU 440SPe RISC 16-Bit 0.13mm 533MHz 1.5V/3.3V 675-Pin FCBGA Tray 制造商:AMCC 功能描述:MPU 440SPE RISC 16BIT 0.13MM 533MHZ 1.5V/3.3V 675FCBGA - Trays
PPC440SPE-RNB667C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor
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