參數(shù)資料
型號: PPC440SPE-ANB667C
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: PowerPC 440SPe Embedded Processor
中文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA675
封裝: 27 X 27 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, FCBGA-675
文件頁數(shù): 74/80頁
文件大小: 572K
代理商: PPC440SPE-ANB667C
PowerPC 440SPe Embedded Processor
74
AMCC Proprietary
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
DDR SDRAM Read Operation
The Read of the incoming Data from the SDRAM is done on the rising and falling edges of the differential DQS
signal. The Data must be centered to these edges for correct operation.
The PPC440SPe can delay with very fine granularity the DQS through the programming of the
MCIF0_RODC[RQFD] register field.
DDR SDRAM MemClkOut0 and Read Clock Delay
In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data
path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency.
The data are stored in the 8 Flip Flops of the Stage 1, such that it can be transferred later within a 8X period.
Figure 9. DDR SDRAM Read Data Path
PLB bus
[0:63]
DQ
Data
(x64)
MCIF0_RQDC[RQFD]
Programmed
Read DQS
Delay
Package
pins
Mux
C
D
FF: Flip-Flop
Q2
DQS
(Diff)
DDR 1X Clock
Mux
(x64)
(x64)
Read FIFO
PLB 1X Clock
Stage 2
Stage 1
Stage 3
FF
PLB bus
[64:127]
DQS Rising
Edge Sync
DQS Falling
Edge Sync
Q3
0
2
6
4
Coarse Delay
Cycles
Delay
Driver
Rec
MemDCFdbkD
MemDCFdbkR
Ext FeedBack
Signals
Read Start
Feedback
Data Capture
Window
DDR 1X Clock
MCIF0_RDCC[RDSS]
MCIF0_RFDC[RFFD]
MCIF0_RFDC[RFOS]
Stage 2 Store
Oversampling
DQS aligned
FBK signal
CAS Lat Delay
FeedBack
Signal Gen
Fine Delay
T1 T2 T3 T4
Fine Delay
FF
FF
7
5
3
1
1
0
7
Upper
Lower
FF
Q2_Ovs
FF
+1
Compare
DDR 1X Clock
Oversampling
Clock
Read Latency adjust circuit
C
D
FF
FF
adjust
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