參數(shù)資料
型號: PPC440SP-AFC533C
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: PowerPC 440SP Embedded Processor
中文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, PLASTIC, FCBGA-783
文件頁數(shù): 74/85頁
文件大?。?/td> 615K
代理商: PPC440SP-AFC533C
PowerPC 440SP Embedded Processor
74
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
System Interface
Halt
GPIO00:31
SysClk
SysErr
SysPartSel
SysReset
HISRRst
TestEn
TmrClk
Trace Interface
TrcClk
TrcBS0:2
TrcES0:4
TrcTS0:6
n/a
n/a
n/a
19.1
n/a
19.1
n/a
n/a
19.1
n/a
n/a
n/a
8.7
n/a
8.7
n/a
n/a
8.7
n/a
n/a
async
async
n/a
async
async
async
async
async
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
19.1
19.1
19.1
19.1
8.7
8.7
8.7
8.7
Table 14. I/O Specifications—All Speeds
(Sheet 3 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2.
PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz
and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time
requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
3. These are DDR signals that can change on both the positive and negative clock transitions.
Signal
Input (ns)
Output (ns)
Output Current (mA)
I/O H
(minimum)
Clock
Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I/O L
(minimum)
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