參數(shù)資料
型號(hào)： PPC440SP-AFC533C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 440SP Embedded Processor
中文描述： 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, PLASTIC, FCBGA-783
文件頁數(shù)： 62/85頁
文件大?。?/td> 615K
代理商： PPC440SP-AFC533C
PowerPC 440SP Embedded Processor
62
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
Power
AxGND
Analog ground.
na
na
APxV
DD
Analog voltage—1.5V.
Filtered voltages input for PCI PLLs (analog circuits).
Note:
A separate filter for all analog voltages is
recommended.
na
na
AxV
DD
Analog voltage—1.5V.
Filtered voltages input for system PLLs (analog circuits).
Note:
A separate filter for all analog voltages is
recommended.
na
na
GND
Logic and I/O ground.
na
na
OV
DD
I/O supply (except DDR SDRAM and PCI-X)— 3.3V.
na
na
PxV
DD
PCI-X I/O voltage supply.
Note:
PCI-X operates at 3.3V.
PCI-X 266 DDR operates at 1.5V
na
na
SV
DD
DDR SDRAM I/O voltage supply.
Note:
DDR SDRAM operates at 2.5V
DDR2 SDRAM operates as 1.8V
na
na
V
DD
Logic voltage supply—1.5V.
na
na
PSRO
PSRO
Performance Screen Ring Oscillator.
Note:
All PSRO signals should be connected to logic
ground (GND).
na
na
Reserved
Reserved
Do not connect voltage, ground, or any signals to these
pins.
na
na
Table 6. Signal Functional Description (Sheet 7 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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