參數(shù)資料
型號： PPC440SP-AFC533C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 440SP Embedded Processor
中文描述： 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, PLASTIC, FCBGA-783
文件頁數(shù)： 72/85頁
文件大?。?/td> 615K
代理商： PPC440SP-AFC533C
PowerPC 440SP Embedded Processor
72
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
Table 14. I/O Specifications—All Speeds
(Sheet 1 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2.
PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz
and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time
requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
3. These are DDR signals that can change on both the positive and negative clock transitions.
Signal
Input (ns)
Output (ns)
Output Current (mA)
I/O H
(minimum)
Clock
Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I/O L
(minimum)
PCI-X Interfaces
PCIX0:2Ack64
PCIX0:1AD63:00
PCIX2AD31:00
PCIX0:1BE7:0
PCIX2BE3:0
PCIX0:2CalG0:1
PCIX0:1CalR0:1
PCIX0:2Cap
PCIX0:2Clk
PCIX0:2DevSel
PCIX0:2ECC5:2
PCIX0:2Frame
PCIX0:2Gnt0
PCIX0:2Gnt1
PCIX0:1Gnt2:3
PCIX0:2IDSel
PCIX0:2INTA
PCIX0:2IRDY
PCIX0:1M66En
PCIX0:2Par
PCIX0:1Par64
PCIX0:2PErr
PCIX0:1Req0
PCIX0:1Req1:3
PCIX2Req1
PCIX0:2Req64
PCIX0:2Reset
PCIX0:2SErr
PCIX0:2Stop
PCIX0:2TRDY
PCIX0:2VC
Note 2 (2)
0.5(0)
3.5(6)
0.7 (Note 2)
0.5
1.5
PCIX0:2Clk
2
Note 2 (2)
0.5(0)
3.5(6)
0.7 (Note 2)
0.5
1.5
PCIX0:2Clk
2
Note 2 (2)
0.5(0)
3.5(6)
0.7 (Note 2)
0.5
1.5
PCIX0:2Clk
2
Note 2 (2)
dc
Note 2 (2)
Note 2 (2)
Note 2 (2)
na
na
na
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
0.5(0)
dc
0.5(0)
0.5(0)
0.5(0)
na
na
na
0.5(0)
0.5(0)
0.5(0)
0.5(0)
0.5(0)
0.5(0)
0.5(0)
0.5(0)
0.5(0)
0.5(0)
na
na
na
na
na
na
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
na
0.5
0.5
0.5
na
na
na
na
na
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
na
1.5
1.5
1.5
na
na
na
PCIX0:2Clk
2
async
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3.5(6)
3.5(6)
3.5(6)
3.5(6)
3.5(6)
3.5(6)
3.5(6)
3.5(6)
3.5(6)
na
3.5(6)
3.5(6)
3.5(6)
na
na
na
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
na
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
na
na
na
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
na
na
na
na
na
na
PCIX0:2Clk
2
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
Note 2 (2)
0.5(0)
0.5(0)
0.5(0)
0.5(0)
0.5(0)
0.5(0)
3.5(6)
3.5(6)
3.5(6)
3.5(6)
3.5(6)
3.5(6)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.5
1.5
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
PCIX0:2Clk
2
2
2
2
2
2
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