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參數(shù)資料
| 型號： | PPC440SP-AFC533C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PowerPC 440SP Embedded Processor |
| 中文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 60/85頁 |
| 文件大?。?/td> | 615K |
| 代理商： | PPC440SP-AFC533C |
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PowerPC 440SP Embedded Processor
60
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
UART Peripheral Interface
UARTSerClk
Serial clock input that provides an alternative to the
internally generated serial clock. Used in cases where
the allowable internally generated clock rates are not
satisfactory.
I
3.3V LVTTL
1, 4
UART0_Rx
UART0 Receive data.
I
3.3V LVTTL
1, 4
UART0_Tx
UART0 Transmit data.
O
3.3V LVTTL
4
UART0_DCD
UART0 Data Carrier Detect.
I
3.3V LVTTL
6
UART0_DSR
UART0 Data Set Ready.
I
3.3V LVTTL
6
UART0_CTS
UART0 Clear To Send.
I
3.3V LVTTL
1, 4
UART0_DTR
UART0 Data Terminal Ready.
O
3.3V LVTTL
4
UART0_RTS
UART0 Request To Send.
O
3.3V LVTTL
4
UART0_RI
UART0 Ring Indicator.
I
3.3V LVTTL
w/pull-up
1, 4
UART1_Rx
UART1 Receive data.
I
3.3V LVTTL
1, 4
UART1_Tx
UART1 Transmit data.
O
3.3V LVTTL
1, 4
UART1_DSR/CTS
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
I
3.3V LVTTL
1, 4
UART1_DTR/RTS
UART1 Request To Send or Data Terminal Ready. The
choice is determined by a DCR register bit setting.
O
3.3V LVTTL
1, 4
UART2_Rx
UART2 Receive data.
I
3.3V LVTTL
1, 4
UART2_Tx
UART2 Transmit data.
O
3.3V LVTTL
1, 4
IIC Peripheral Interface
IIC0SClk
IIC0 Serial Clock.
I/O
3.3V IIC
1, 2
IIC0SDA
IIC0 Serial Data.
I/O
3.3V IIC
1, 2
IIC1SClk
IIC1 Serial Clock.
I/O
3.3V IIC
1, 2
IIC1SDA
IIC1 Serial Data.
I/O
3.3V IIC
1, 2
Interrupts Interface
IRQ0:5
External interrupt Requests 0 through 5.
I
3.3V LVTTL
1, 5
Table 6. Signal Functional Description (Sheet 5 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
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| PPC440SP-AFC667C | PowerPC 440SP Embedded Processor |
| PPC440SP-ANC533C | PowerPC 440SP Embedded Processor |
| PPC440SP-ANC667C | PowerPC 440SP Embedded Processor |
| PPC440SP-RFC533C | PowerPC 440SP Embedded Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440SP-AFC667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SP Embedded Processor |
| PPC440SP-ANC533C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SP Embedded Processor |
| PPC440SP-ANC667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SP Embedded Processor |
| PPC440SPE | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
| PPC440SPE-3GA533C | 制造商:AppliedMicro 功能描述: |
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