參數(shù)資料
型號(hào)： PPC440GR-3pbfffCx
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GR Embedded Processor
中文描述： 440GR的Power PC嵌入式處理器
文件頁(yè)數(shù)： 73/82頁(yè)
文件大?。?/td> 527K
代理商： PPC440GR-3PBFFFCX
AMCC Proprietary
73
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Revision 1.16 – July 19, 2006
Note:
The timing data in the following tables is based on simulation runs using Einstimer.
Table 20. I/O Timing—DDR SDRAM T
DS
Notes:
1. All of the DQS signals are referenced to MemClkOut0(0).
2. Clock speed is 133MHz.
3. The T
DS
values in the table include 3/4 of a cycle at 133MHz (7.5ns x 0.75 = 5.625 ns).
4. To obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle
time for the lower clock frequency (T
DS
- 5.625 + 0.75T
CYC
).
Table 21. I/O Timing—DDR SDRAM T
SK
, T
SA
, and T
HA
Notes:
1. Clock speed is 133MHz. T
SK
is referenced to MemClkOut0(0). T
SA
and T
HA
are referenced to MemClkOut0(90).
2. To obtain adjusted T
SA
values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and subtract
T
SK
maximum (0.75T
CYC
- T
SK
max).
3. To obtain adjusted T
HA
values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add
T
SK
minimum (0.25T
CYC
+ T
SK
min).
Table 22. I/O Timing—DDR SDRAM T
SD
and T
HD
Notes:
1. T
SD
and T
HD
are measured under worst case conditions.
2. Clock speed for the values in the table is 133MHz.
3. The time values in the table include 1/4 of a cycle at 166MHz (7.5ns x 0.25 = 1.875 ns).
4. To obtain adjusted T
SD
and T
HD
values for lower clock frequencies, subtract 1.875 ns from the values in the table and add
1/4 of the cycle time for the lower clock frequency (e.g., T
SD
- 1.875 + 0.25T
CYC
).
Signal Name
T
DS
(ns)
Minimum
5.76
5.78
5.82
5.79
5.75
Maximum
5.86
5.91
5.90
5.89
5.88
DQS0
DQS1
DQS2
DQS3
DQS8
Signal Name
T
SK
(ns)
T
SA
(ns)
Minimum
5.31
5.32
5.38
5.35
5.32
5.35
5.41
T
HA
(ns)
Minimum
1.99
1.95
1.93
1.95
1.93
1.93
1.96
Minimum
0.11
0.07
0.05
0.07
0.05
0.05
0.08
Maximum
0.32
0.31
0.25
0.28
0.31
0.28
0.22
MemAddr00:12
BA0:1
BankSel0:3
ClkEn0:3
CAS
RAS
WE
Signal Names
Reference Signal
DQS0
DQS1
DQS2
DQS3
DQS8
T
SD
(ns)
1.795
1.775
1.745
1.765
1.685
T
HD
(ns)
1.866
1.865
1.862
1.864
1.857
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
ECC0:7, DM8
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