參數(shù)資料
型號: PPC440GR-3pbfffCx
廠商: Applied Micro Circuits Corp.
英文描述: Power PC 440GR Embedded Processor
中文描述: 440GR的Power PC嵌入式處理器
文件頁數(shù): 56/82頁
文件大?。?/td> 527K
代理商: PPC440GR-3PBFFFCX
56
AMCC Proprietary
Revision 1.16 – July 19, 2006
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
System Interface
SysClk
Main system clock input.
Clock
3.3V LVTTL
SysErr
Set to 1 when a machine check is generated.
O
3.3V tolerant
2.5V CMOS
SysReset
Main system reset. External logic can drive this bidirectional
pin low (minimum of 16 cycles) to initiate a system reset. A
system reset can also be initiated by software. Implemented as
an open-drain output (two states; 0 or open circuit).
I/O
3.3V tolerant
2.5V CMOS
1, 2
Halt
Halt from external debugger.
I
3.3V LVTTL
1, 4
TmrClk1
Processor timer external input clock.
I
3.3V tolerant
2.5V CMOS
TmrClk2
This signal must be connected to a clock. It can be connected
to any available clocking signal in the frequency range of
32kHz to 100MHz including TmrClk1.
I
3.3V tolerant
2.5V CMOS
GPIO00:63
General purpose I/O 0 through 63. To access these functions,
software must set DCR register bits.
I/O
Multiplex
TestEn
Test Enable.
I
Multiplex
3
RcvrInh
Receiver Inhibit. Active only when TestEn is active.
I
Multiplex
ModeCtrl
Mode Control.
I
Multiplex
LeakTest
Leakage Test.
I
Multiplex
RefEn
Reference Enable.
I
Multiplex
DrvrInh1:2
Driver Inhibit. Used for test purposes only. Tie up as specified
in Note 2 for normal operation.
I
3.3V tolerant
2.5V CMOS
2
PSROOut
Module characterization and screening.
O
Perf screen
ring osc
1, 3
Table 7. Signal Functional Description (Sheet 7 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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