參數(shù)資料
型號(hào)： PPC440GR-3pbfffCx
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GR Embedded Processor
中文描述： 440GR的Power PC嵌入式處理器
文件頁(yè)數(shù)： 10/82頁(yè)
文件大小： 527K
代理商： PPC440GR-3PBFFFCX
10
AMCC Proprietary
Revision 1.16 – July 19, 2006
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
Internal Buses
The PowerPC 440GR features four standard on-chip buses: two Processor Local Buses (PLBs), one On-Chip
Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores
such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI bridge connect to the
PLBs. The primary OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth
path for passing status and control information between the processor core and the other on-chip cores.
Features include:
PLB 128 (PLB4)
– 128-bit implementation of the PLB architecture
– Separate and simultaneous read and write data paths
– 36-bit address
– Simultaneous control, address, and data phases
– Four levels of pipelining
– Byte-enable capability supporting unaligned transfers
– 32- and 64-byte burst transfers
– 133MHz, maximum 4.25GB/s (simultaneous read and write)
– Processor:bus clock ratios of N:1 and N:2
PLB 64 (PLB3)
– 64-bit implementation of the PLB architecture
– 32-bit address
– 133MHz (1:1 ratio with PLB 128), maximum 1.1GB/s (no simultaneous read and write)
OPB
– 32-bit data path
– 32-bit address
– 66.66MHz
DCR
– 32-bit data path
– 10-bit address
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