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參數(shù)資料
| 型號(hào)： | PPC440GR-3pbfffCx |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Power PC 440GR Embedded Processor |
| 中文描述： | 440GR的Power PC嵌入式處理器 |
| 文件頁數(shù)： | 50/82頁 |
| 文件大?。?/td> | 527K |
| 代理商： | PPC440GR-3PBFFFCX |
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50
AMCC Proprietary
Revision 1.16 – July 19, 2006
Preliminary Data Sheet
440GR – PPC440GR Embedded Processor
Table 7. Signal Functional Description (Sheet 1 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
PCI Interface
PCIAD00:31
Address/Data bus (bidirectional).
I/O
3.3V PCI
PCIC0:3/BE0:3
PCI Command/Byte Enables
.
I/O
3.3V PCI
PCIClk
Provides timing to the PCI interface for PCI transactions.
I
3.3V PCI
PCIDevSel
Indicates the driving device has decoded its address as the
target of the current access.
I/O
3.3V PCI
PCIFrame
Driven by the current master to indicate beginning and
duration of an access.
I/O
3.3V PCI
PCIGnt1/Req
Indicates that the specified agent is granted access to the bus.
When the internal arbiter is enabled, output is PCIGnt0. When
the internal arbiter is disabled, output is Req.
O
3.3V PCI
PCIGnt2:6
Indicates that the specified agent is granted access to the bus.
O
3.3V PCI
PCIIDSel
Used as a chip select during configuration read and write
transactions.
I
3.3V PCI
PCIINT
Level sensitive PCI interrupt.
O
3.3V PCI
PCIIRDY
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
I/O
3.3V PCI
PCIPar
Even parity.
I/O
3.3V PCI
PCIPErr
Reports data parity errors during all PCI transactions except a
Special Cycle.
I/O
3.3V PCI
PCIReq0/Gnt
Indicates to the PCI arbiter that the specified agent wishes to
use the bus. When the internal arbiter is enabled, input is
PCIReq0. When internal arbiter is disabled, input is Gnt.
I
3.3V PCI
PCIReq1:5
An indication to the PCI arbiter that the specified agent wishes
to use the bus.
I
3.3V PCI
PCIReset
Brings PCI device registers and logic to a consistent state.
O
3.3V PCI
PCISErr
Reports address parity errors, data parity errors on the Special
Cycle command, or other catastrophic system errors.
I/O
3.3V PCI
PCIStop
Indicates the current target is requesting the master to stop the
current transaction.
I/O
3.3V PCI
PCITRDY
I
ndicates the target agent’s ability to complete the current data
phase of the transaction.
I/O
3.3V PCI
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|---|---|
| PPC440GRx-NpAfffTs | PowerPC 440GRx Embedded Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440GRX-NPAFFFTS | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440GRx Embedded Processor |
| PPC440GRX-NTA400E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440GRX-NTA400EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440GRX-NTA533EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440GRX-NTA667EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
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