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參數(shù)資料
| 型號(hào)： | PPC440GR-3pbfffCx |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Power PC 440GR Embedded Processor |
| 中文描述： | 440GR的Power PC嵌入式處理器 |
| 文件頁數(shù)： | 53/82頁 |
| 文件大?。?/td> | 527K |
| 代理商： | PPC440GR-3PBFFFCX |
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AMCC Proprietary
53
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Revision 1.16 – July 19, 2006
External Slave Peripheral Interface
DMAAck0:3
Used by the PPC440GR to indicate that data transfers have
occurred.
O
Multiplex
DMAReq0:3
Used by slave peripherals to indicate they are prepared to
transfer data.
I
Multiplex
1, 5
EOT0:3/TC0:3
End Of Transfer/Terminal Count.
I/O
Multiplex
1, 5
PerAddr02:07
Peripheral address bus used by PPC440GR when not in
external master mode, otherwise used by external master.
I/O
3.3V LVTTL
1, 2
PerAddr08:31
Peripheral address bus used by PPC440GR when not in
external master mode, otherwise used by external master.
I/O
3.3V LVTTL
PerBLast
Used by either the peripheral controller, DMA controller, or
external master to indicates the last transfer of a memory
access.
I/O
3.3V LVTTL
1, 4
PerCS0:5
External peripheral device select.
O
3.3V LVTTL
2
PerData00:15
Peripheral data bus used by PPC440GR when not in external
master mode, otherwise used by external master.
Note:
PerData00 is the most significant bit (msb) on this bus.
I/O
3.3V LVTTL
1
PerOE
Used by either peripheral controller or DMA controller
depending upon the type of transfer involved. When the
PPC440GR is the bus master, it enables the selected device to
drive the bus.
O
3.3V LVTTL
2
PerReady
Used by a peripheral slave to indicate it is ready to transfer
data.
I
3.3V LVTTL
PerR/W
Used by the PPC440GR when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
Otherwise, it used by the external master as an input to
indicate the direction of transfer.
I/O
3.3V LVTTL
1, 2
PerWBE0:1
External peripheral data bus byte enables.
I/O
3.3V LVTTL
1, 2
PerErr
External Error. Used as an input to record external slave
peripheral errors.
I/O
3.3V LVTTL
1, 5
Table 7. Signal Functional Description (Sheet 4 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440GRx-NpAfffTs | PowerPC 440GRx Embedded Processor |
| PPC440GRx-SpAfffTs | PowerPC 440GRx Embedded Processor |
| PPC440GX-3RF800CZ | Power PC 440GX Embedded Processor |
| PPC440GX-3CC533S | Power PC 440GX Embedded Processor |
| PPC440GX-3CC667S | Power PC 440GX Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440GRX-NPAFFFTS | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440GRx Embedded Processor |
| PPC440GRX-NTA400E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440GRX-NTA400EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440GRX-NTA533EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440GRX-NTA667EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
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